PL133-67OI Datasheet PL133-67OI, PL133-67OC, PL133-67OI-R | P1-P3

PL133-67

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC

Mic rel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 1

FEATURES

 1:6 LVCMOS output fanout buffer for DC to 150MHz

 8mA Output Drive Strength

 Low power consumption for portable applications

 Low input-output delay

 Output-Output skew less than 250ps

 Low Additive Phase Jitter of 60fs RMS

 2.5V to 3.3V, ±10% operation

 Operating temperature range from -40°C to 85°C

 Available in 16-Pin SOP GREEN/RoHS package

DESCRIPTION

The PL133-67 is an advanced fanout buffer design for

high performance, low-power, small form factor applica-

tions. The PL133-67 accepts a reference clock input from

DC to 150MHz and provides 6 outputs of the same fre-

quency.

The PL133-67 is offered in a TSSOP-16L package and it

offers the best phase noise, additive jitter performance,

and lowest power consumption of any comparable IC.

The PL133-67 outputs can be disabled to a high imped-

ance (tri-state) by pulling low the OE pin. When the OE pin

is high, the outputs are enabled and follow the REF input

signal. When the OE pin is left open, a pull-up resistor on

the chip will default the OE pin to logic 1 so the outputs are

enabled.

BLOCK DIAGRAM AND PACKAGE PINOUT

REF

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

1REF

DNC

CLK0

VDD

DNC

CLK5

VDD

GND

CLK4

CLK3

GND

10

11

12

13

14

15

16

98

7

6

5

4

3

2

OE^

CLK2

CLK1

GND

TSSOP-16L

OE

PL133-67

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC

Mic rel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 2

PIN DESCRIPTIONS

Name

TSSOP-16L

Type

Description

REF

1

I

Input reference frequency.

CLK0

3

O

Buffered clock output

CLK1

6

O

Buffered clock output

CLK2

7

O

Buffered clock output

CLK3

10

O

Buffered clock output

CLK4

11

O

Buffered clock output

CLK5

14

O

Buffered clock output

VDD

4, 13

P

VDD connection

GND

5, 9, 12

P

GND connection

OE

8

I

Output Enable Control Input with 130K Pull-Up

DNC

2, 8, 15, 16

-

Do Not Connect

LAYOUT RECOMMENDATIONS

The following guidelines are to assist you with a performance optimized PCB d esign:

Signal Integrity and Termination

Considerations

- Keep traces short!

- Trace = Inductor. With a capacitive load this equals

ringing!

- Long trace = Transmission Line. Without proper termi-

nation this will cause reflections ( looks like ringing ).

- Design long traces (> 1 inch) as “striplines” or

“microstrips” with defined impedance.

- Match trace at one side to avoid reflections bouncing

back and forth.

Decoupling and Power Supply

Considerations

- Place decoupling capacitors as close as possible

to the VDD pin(s) to limit noise from the power

supply

- Addition of a ferrite bead in series with VDD can

help prevent noise from other board sources

- Value of decoupling capacitor is frequency de-

pendant. Typical values to use are 0.1F for de-

signs using frequencies < 50MHz and 0.01F for

designs using frequencies > 50MHz.

Typical CMOS termination

Place Series Resistor as close as possible to CMOS output

CMOS Output Buffer

( Typical buffer impedance 20 ohm)

To CMOS Input

Connect a 33 ohm series resistor at each of the output clocks to

enhance the stability of the output signal

50 ohm line

PL133-67

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC

Mic rel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/18/11 Page 3

ABSOLUTE MAXIMUM CONDITIONS

Supply Voltage to Ground Potential ...... –0.5V to 4.6V

DC Input Voltage ............................ V

SS

– 0.5V to 4.6V

Storage Temperature ..........................–65°C to 150°C

Junction Temperature………………………….. 150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015)…………..> 2000V

OPERATING CONDITIONS

Parameter

Description

Min.

Max.

Unit

V

DD

Supply Voltage

2.25

3.63

V

T

A

Commercial Operating Temperature (ambient te mperature)

0

70

C

Industrial Operating Temperature (ambient temperature)

-40

85

C

C

L

Load Capacitance, below 100 MHz

―

30

pF

Load Capacitance between 100 MHz and 134 MHz

―

10

pF

Load Capacitance, above 134 MHz

―

5

pF

C

IN

Input Capacitance

―

7

pF

REF, CLK[1:6]

Operating Frequency, Input=Output

DC

150

MHz

t

PU

Power-up time for all V

DD

s to reach minimum specified voltage

(power ramps must be monotonic)

0.05

50

ms

ELECTRICAL CHARACTERISTICS (Commercial and Industrial Temperature Devices)

Parameter

Description

Test Conditions

Min.

Max.

Unit

V

IL

Input LOW Voltage

[1]

–

0.8

V

IH

Input HIGH Voltage

[1]

2.0

–

V

I

IL

Input LOW Current

V

IN

= 0V

–

50

µA

I

IH

Input HIGH Current

V

IN

= V

DD

–

100

µA

V

OL

Output LOW Voltage

[2]

I

OL

= 8 mA

–

0.4

V

OH

Output HIGH Voltage

[2]

I

OH

= –8 mA

2.4

–

V

I

DD

Supply Current

66.67MHz with unloaded outputs

–

32

mA

R

PU

OE Pin Pull-Up Resistance

100

–

K

PL133-67OI

PL133-67OI

Products related to this Datasheet