BUK9212-55B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 03 — 3 February 2011 3 of 13
NXP Semiconductors
BUK9212-55B
N-channel TrenchMOS logic level FET
4. Limiting values
[1] Current is limited by power dissipation chip rating.
[2] Continuous current is limited by package.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 185 °C - 55 V
V
DGR
drain-gate voltage R
GS
=20kΩ -55V
V
GS
gate-source voltage -15 15 V
I
D
drain current T
mb
=25°C; V
GS
=5V; see Figure 1;
see Figure 3
[1]
-83A
[2]
-75A
T
mb
=100°C; V
GS
=5V; see Figure 1
[1]
-59A
I
DM
peak drain current T
mb
= 25 °C; pulsed; t
p
≤ 10 µs;
see Figure 3
- 335 A
P
tot
total power dissipation T
mb
=25°C; see Figure 2 - 167 W
T
stg
storage temperature -55 185 °C
T
j
junction temperature -55 185 °C
Source-drain diode
I
S
source current T
mb
=25°C
[1]
-83A
[2]
-75A
I
SM
peak source current pulsed; t
p
≤ 10 µs; T
mb
= 25 °C - 335 A
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source
avalanche energy
I
D
=75A; V
sup
≤ 55 V; R
GS
=50Ω;
V
GS
=5V; T
j(init)
= 25 °C; unclamped
- 173 mJ
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
03nl11
0
25
50
75
100
0 50 100 150 200
I
D
(A)
Capped at 75A due to package
T
mb
(°C)
03no96
0
40
80
120
0 50 100 150 200
T
mb
(
°
C)
P
der
(%)
