FAN5059 PRODUCT SPECIFICATION
16 REV. 1.0.4 8/14/03
Appendix
Worst-Case Formulae for the Calculation of
Cin, Cout , R5, R7 and Roffset
(Circuits similar to
Figure 1 only)
The following formulae design the FAN5059 for worst-case
operation, including initial tolerance and temperature dependence
of all of the IC parameters (initial setpoint, reference tolerance
and tempco, internal droop impedance, current sensor gain),
the initial tolerance and temperature dependence of the MOSFET,
and the ESR of the capacitors. The following information
must be provided:
V
S+
, the value of the positive static voltage limit;
|V
S-
|, the absolute value of the negative static voltage limit;
V
T+
, the value of the positive transient voltage limit;
|V
T-
|, the absolute value of the negative transient voltage limit;
I
O
, the maximum output current;
V
nom
, the nominal output voltage;
V
in
, the input voltage (typically 5V);
I
rms
, the ripple current rating of the input capacitors, per cap
(2A for the Sanyo parts shown in this datasheet);
R
D
, the resistance of the current sensor (usually the MOSFET);
R
D
, the tolerance of the current sensor (usually about 67%
for MOSFET sensing, including temperature); and
ESR, the ESR of the output capacitors, per cap (44m for
the Sanyo parts shown in this datasheet).
The value of R7 must be 8.3K. If a greater value is calcu-
lated, R
D
must be reduced.
Number of capacitors needed for C
out
= the greater of:
Example: Suppose that the static limits are +89mV/-79mV,
transient limits are ±134mV, current I is 14.2A, and the
nominal voltage is 2.000V, using MOSFET current sensing.
We have V
S+
= 0.089, |V
S-
| = 0.079, V
T+
= |V
T-
| = 0.134, I
O
= 14.2, V
nom
= 2.000, and R
D
= 1.67. We calculate:
Since Y > X, we choose Y, and round up to find we need 7
capacitors for C
OUT
.
A detailed explanation of this calculation may be found in
Applications Bulletin AB-24.
2
I
rms
1.01 * V
nom
V
in
V
nom
V
in
V
nom
*IO
C
in
=
45 * 10
-
6
I
O
* R
D
* (1 + R
D
)
R7
* 1K
=
V
S+
– .024 * V
nom
R
offset
=
18 * (V
S+
+ V
S-
– .024 * V
nom
)
14400 * I
O
* R
D
* (1 + R
D
) *1.1
R5 =
V
T-
+ V
S+
– .024 * V
nom
ESR * I
O
ESR * I
O
X=
18 * R5 * 1.1
14400 * I
O
* R
D
Y
or
V
T+
– V
S+
+
=
2
5
2.000
5
2.000
*14.2
C
in
2
3.47 4 caps
=
=
=
=
3.48K
18 * (0.089 + 0.079 – .024 * 2.000)
14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1
R5
=
=
5.25K
45 * 10
-6
14.2 * 0.010 * (1 + 0.67)
R7
=
=
20.3*1000
1.01 * 2.000
0.089 – .024 * 2.000
R
offset
3.57
0.134 + 0.089 – .024 * 2.00
0.044 * 14.2
X
=
=
6.14
18 * 3640 * 1.1
14400 * 14.2 * 0.020
0.134 – 0.089
0.044 * 14.2
Y
=
+
=
PRODUCT SPECIFICATION FAN5059
REV. 1.0.4 8/14/03 17
Mechanical Dimensions
24 Lead SOIC
24 13
112
A .093 .104 2.35 2.65
Symbol
Inches
Min. Max. Min. Max.
Millimeters
Notes
A1 .004 .012 0.10 0.30
.020 0.51
B .013 0.33
C .009 .013 0.23 0.32
E .290 .299 7.36 7.60
e
.394 .419 10.00 10.65
.010 .020 0.25 0.51
H
.050 BSC 1.27 BSC
h
L .016 .050 0.40 1.27
0° 8° 0° 8°
3
6
5
2
2
N24 24
α
ccc .004 0.10——
D .599 .614 15.20 15.60
Notes:
1.
2.
3.
4.
5.
6.
Dimensioning and tolerancing per ANSI Y14.5M-1982.
"D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .010 inch (0.25mm).
"L" is the length of terminal for soldering to a substrate.
Terminal numbers are shown for reference only.
"C" dimension does not include solder finish thickness.
Symbol "N" is the maximum number of terminals.
H
E
A
D
e
B
A1
– C –
ccc C
LEAD COPLANARITY
SEATING
PLANE
α
h x 45°
L
C
FAN5059 PRODUCT SPECIFICATION
8/14/03 0.0m 012
Stock#DS30005059
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Ordering Information
Product Number Package
FAN5059M 24 pin SOIC

FAN5059M

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
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