EVAL-ADXL354/EVAL-ADXL355 User Guide UG-1030
Rev. 0 | Page 3 of 5
EVALUATION BOARD HARDWARE
The E VA L -ADXL354BZ, E VA L -ADXL354CZ, and EVA L-
ADXL355Z evaluation boards allow users to access the individual
connections of the ADXL354 and ADXL355. Each of the
evaluation boards include decoupling capacitors for supplies, a
few discrete resistors to provide isolation on the V
1P8ANA
and
V
1P8DIG
pins, and two 6-pin headers. Refer to the ADXL354/
ADXL355 data sheet for more detail on specific pin definitions.
The power supplies for the ADXL354/ADXL355 is decoupled
using multiple 0.1 μF ceramic (0603) capacitors.
The E VA L -ADXL354BZ and E VA L -ADXL354CZ evaluation
boards have capacitors on each axis output to set the output
low-pass filter and two 3-position jumpers to configure Range
and Mode. The two 6-pin headers provide access to all other
pins. Header P1 provides access to V
DDIO
(sets the RANGE pin
and the
STBY
pin levels on the EVA L-ADXL354BZ and E VA L -
ADXL354CZ evaluation boards), VDD (supplies the ADXL354
V
SUPPLY
pin), V
SS
/V
SSIO
(supplies the ground connection), X
OUT
,
Y
OUT
, and Z
OUT
, shown in Figure 3. Header P2 provides access to
V
1P8ANA
, V
1P8DIG
, TEM P, S T 1, ST2, and V
SS
(supplies the ground
connection), shown in Figure 4.
Figure 3. EVAL-ADXL354BZ and EVAL-ADXL354CZ Function Block Diagram
for Header P1
Figure 4. EVAL-ADXL354BZ and EVAL-ADXL354CZ Function Block Diagram
for Header P2
The E VA L-ADXL355Z uses two 6-pin headers to provide access
to all pins. Header P1 provides access to V
DDIO
, VDD (which is
connected to the ADXL355 V
SUPPLY
pin), V
SS
/V
SSIO
(supply ground
connection), INT1, INT2, and DRDY, shown in Figure 5.
Header P2 provides access to V
1P8ANA
, V
1P8DIG
, MISO/ASEL,
CS
/SCL, SCLK/V
SSIO
, and MOSI/SDA (see Figure 6).
Figure 5. EVAL-ADXL355Z Function Block Diagram for Header P1
Figure 6. EVAL-ADXL355Z Function Block Diagram for Header P2
The vias or headers allow the evaluation boards to attach to
either a prototyping breadboard or to a printed circuit board
(PCB) in an existing user system. Four holes are provided in the
corners of the evaluation board for mechanical attachment of the
evaluation boards in many applications. An external host processor
is required for communication to the ADXL355, while the analog
output of the ADXL354 must be connected to a band limited
analog-to-digital converter (ADC).
The dimensions of the evaluation boards are 0.8 in × 0.8 in.
CIRCUIT DESCRIPTION
The PCB layout of the EVA L -ADXL354BZ, EVA L-ADXL354CZ,
and E VA L -ADXL355Z evaluation boards are shown in Figure 2.
The ADXL354 and ADXL355 each have two moded by which
they can be powered: by integrated low dropout regulators (LDOs)
or external, user supplied 1.8 V regulated supplies. Refer to the
ADXL354/ADXL355 data sheet for more information.
HANDLING CONSIDERATIONS
The E VA L -ADXL354BZ, E VA L -ADXL354CZ, and E VA L -
ADXL355Z evaluation boards are not reverse polarity protected.
Reversing any of the supply connections, including the V
SS
and
V
SSIO
pins, can cause damage to the ADXL354/ADXL355.
Dropping the evaluation boards on a hard surface can generate
several thousand g of acceleration, which can exceed the
ADXL354/ADXL355 data sheet absolute maximum limits.
1
3
5
2
4
6
X
OUT
Y
OUT
Z
OUT
P1
202-187
V
DDIO
VDD
14832-003
1
3
5
V
1P8ANA
V
1P8DIG
TEMP
2
4
6
ST1
ST1
P2
202-187
14832-004
1
3
5
2
4
6
INT1
INT2
DRDY
P1
202-187
V
DDIO
VDD
14832-005
1
3
5
2
4
6
CS/SCL
SCLK/V
SSIO
MOSI/SDA
V
1P8ANA
V
1P8DIG
MISO/SDA
P2
202-187
14832-006
