MT9043 Data Sheet
3
Zarlink Semiconductor Inc.
5 SEC Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources
(falling edge) used for synchronization. One of four possible frequencies (8 kHz, 1.544 MHz,
2.048 MHz or 19.44 MHz) may be used. The selection of the input reference is based upon
the MS, and RSEL, control inputs.This pin is internally pulled up to V
DD
.
6PRIPrimary Reference (Input). See pin description for SEC. This pin is internally pulled up to
V
DD
.
7,17
28,35
V
DD
Positive Supply Voltage. +3.3V
DC
nominal.
8OSCoOscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 9. Not suitable for driving other devices. For
clock oscillator operation, this pin is left unconnected, see Figure 8.
9OSCiOscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 9. For clock oscillator operation, this pin is
connected to a clock source, see Figure 8.
11 F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s. See Figure 14.
12 F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 14.
13 RSP Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
14 TSP Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 15.
15 F8o Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse, which
marks the beginning of a frame. See Figure 14.
16 C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
19 C2o Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.
20 C4o
Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
21 C19o Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.
22 FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
24 IC Internal Connection. Tie low for normal operation.
25 C8o Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.
26 C16o
Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
Pin Description
Pin # Name Description