MP6400 -- LOW QUIESCENT CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT
MP6400 Rev. 1.1 www.MonolithicPower.com 9
12/27/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
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APPLICATION INFORMATION
Reset Output Function
The MP6400 output is typically connected
to the
input of a microprocessor, as shown
in Figure 3. When
is not asserted, a pull
up resistor must be connected to hold this signal
high. The voltage of reset signal is allowed to be
higher than V
CC
(up to 6V) through a resistor
pulling up from supply line. If the voltage is below
0.8V,
output is undefined. This condition
can be ignored generally because that most
microprocessors do not function at this state.
When both SENSE and
are higher than their
threshold voltage,
output holds logic high.
Once either of the two drops below their
threshold,
will be asserted.
V
CC
R1
VCC
SENSE
MR
GND
C
DELAY
C
DELAY
47pF
GND
RESET
RESET
R2
Microprocessor
DSP
Microcontroller
0.1uF
1nF
100k
Figure 3—Typical Application of MP6400 with
Microprocessor
From the point that is again logic high and
SENSE is above V
IT
+ V
HYS
(the threshold
hysteresis),
will be driven to a logic high
after a reset delay time. The reset delay time is
programmable by C
DELAY
pin. Due to the finite
impedance of
pin, the pull up resistor
should be bigger than 10kΩ.
Monitor a Voltage
The SENSE input pin is connected to the
monitored system voltage directly or through a
resistor network (on MP6400DJ-01). When the
voltage on the pin is below V
IT
, is asserted.
A threshold hysteresis will prevent the chip from
responding perturbation on SENSE pin. A 1nF to
10nF bypass capacitor should be put on this pin
to increase its immunity to noise. A typical
application of the MP6400DJ-01 is shown in
Figure 4. Two external resistors form a voltage
divider from monitored voltage to GND. Its tap
connects to the SENSE pin. The circuit can be
used to monitor any voltage higher than 0.4V.
VCC
SENSE
GND
R2
1nF
R1
V
SEN
V
OUT
V
IT
= (1+ )
R1
R2
0.4
MP6400DJ-01
RESET
Figure 4—MP6400DJ-01 Monitoring a User-
Defined Voltage
Monitor Multiple System Voltages
The manual reset ( ) can introduce another
logic signal to control the
. When is a
logic low (0.25V
CC
), will be asserted. After
both SENSE and
are above their thresholds,
will be driven to a logic high after a reset
delay time. The
is internally connected to V
CC
through a 90kΩ resistor so this pin can float. See
how multiple system voltages are monitored by
in Figure 5. If the signal on isn’t up to V
CC
,
there will be an additional current through internal
90kΩ pull up resistor. A logic-level FET can be
used to minimize the leakage, as shown in Figure
6.
SENSE
1.2V
3.3V
VCC SENSE VCC
GND GND
GND
C
DELAY
C
DELAY
V
I/O
V
CORE
MP6400DJ-12
MP6400DJ-33 DSP
RESET RESET RESET
MR
Figure 5— MP6400 Family Monitoring Multiple
System Voltages
