AD7150
Rev. 0 | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
1
VDD
2
CIN2
3
CIN1
4
EXC2
5
SDA
10
SCL
9
OUT2
8
OUT1
7
EXC1
6
AD7150
TOP VIEW
(Not to Scale)
06517-003
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 GND Ground Pin.
2 VDD
Power Supply Voltage. This pin should be decoupled to GND using a low impedance capacitor, for example,
0.1 μF X7R multilayer ceramic.
3 CIN2
CDC Capacitive Input Channel 2. The measured capacitance (sensor) is connected between the EXC2 pin and
the CIN2 pin. If not used, this pin can be left open circuit or connected to GND.
4 CIN1
CDC Capacitive Input Channel 1. The measured capacitance (sensor) is connected between the EXC1 pin and
the CIN1 pin. If not used, this pin can be left open circuit or connected to GND.
5 EXC2
CDC Excitation Output Channel 2. The measured capacitance is connected between the EXC2 pin and the
CIN2 pin. If not used, this pin should be left as an open circuit.
6 EXC1
CDC Excitation Output Channel 1. The measured capacitance is connected between the EXC1 pin and the
CIN1 pin. If not used, this pin should be left as an open circuit.
7 OUT1 Logic Output Channel 1. A high level on this output indicates proximity detected on CIN1.
8 OUT2 Logic Output Channel 2. A high level on this output indicates proximity detected on CIN2.
9 SCL
Serial Interface Clock Input. Connects to the master clock line. Requires a pull-up resistor if not provided
elsewhere in the system.
10 SDA
Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided
elsewhere in the system.
AD7150
Rev. 0 | Page 7 of 28
25020015010050
OFFSET ERROR (fF)
CAPACITANCE CIN TO GND (pF)
TYPICAL PERFORMANCE CHARACTERISTICS
300
200
100
0
–100
03
00
06517-004
25020015010050
GAIN ERROR (%FS)
CAPACITANCE CIN TO GND (pF)
Figure 4. Capacitance Input Offset Error vs. Capacitance CIN to GND,
V
DD
= 3.3 V, EXC Pin Open Circuit
2
–8
–6
–4
–2
0
03
00
06517-005
25020015010050
GAIN ERROR (%FS)
CAPACITANCE CIN TO GND (pF)
Figure 5. Capacitance Input Gain Error vs. Capacitance CIN to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
2
–8
–6
–4
–2
0
03
00
06517-006
2
–2
–1
0
1
030025020015010050
OFFSET ERROR (fF)
CAPACITANCE EXC TO GND (pF)
06517-007
0.10
–0.10
–0.05
0
0.05
030025020015010050
GAIN ERROR (%FS)
CAPACITANCE EXC TO GND (pF)
Figure 6 .Capacitance Input Gain Error vs. Capacitance CIN to GND,
V
DD
= 3.3 V, CIN to EXC = 10 pF
Figure 7. Capacitance Input Offset Error vs. Capacitance EXC to GND,
V
DD
= 3.3 V, CIN Pin Open Circuit
06517-008
0.10
–0.10
–0.05
0
0.05
030025020015010050
GAIN ERROR (%FS)
CAPACITANCE EXC TO GND (pF)
Figure 8. Capacitance Input Gain Error vs. Capacitance EXC to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
06517-009
Figure 9. Capacitance Input Gain Error vs. Capacitance EXC to GND,
V
DD
= 3.3 V, CIN to EXC = 10 pF
AD7150
Rev. 0 | Page 8 of 28
500
–500
–250
0
250
11
00010010
OFFSET ERROR (fF)
RESISTANCE CIN TO GND (M)
06517-010
Figure 10. Capacitance Input Offset Error vs. Resistance CIN to GND,
V
DD
= 3.3 V, EXC Pin Open Circuit
10
–10
–5
0
5
11
00010010
GAIN ERROR (%FS)
RESISTANCE CIN TO GND (M)
06517-011
8642
OFFSET ERROR (fF)
RESISTANCE EXC TO GND (M)
Figure 11. Capacitance Input Gain Error vs. Resistance CIN to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
10
–10
–5
0
5
01
0
06517-012
0.50
–0.50
–0.25
0
0.25
0108642
GAIN ERROR (%FS)
RESISTANCE EXC TO GND (M)
06517-013
2
–8
–6
–4
–2
0
025020015010050
GAIN ERROR (%FS)
SERIAL RESISTANCE (k)
Figure 12. Capacitance Input Offset Error vs. Resistance EXC to GND,
V
DD
= 3.3 V, CIN Pin Open Circuit
Figure 13. Capacitance Input Gain Error vs. Resistance EXC to GND,
V
DD
= 3.3 V, CIN to EXC = 2 pF
06517-014
Figure 14. Capacitance Input Gain Error vs. Serial Resistance,
V
DD
= 3.3 V, CIN to EXC = 2 pF
10
–10
–5
0
5
1100010010
GAIN ERROR (%FS)
PARALLEL RESISTANCE (M)
06517-015
Figure 15. Capacitance Input Gain Error vs. Parallel Resistance,
V
DD
= 3.3 V, CIN to EXC = 2 pF

AD7150BRMZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Data Acquisition ADCs/DACs - Specialized 2-CH CDC wt adaptive threshold IC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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