LT3514
22
3514fa
For more information www.linear.com/LT3514
APPLICATIONS INFORMATION
Bear in mind that significant power dissipation occurs in
Q1 during an overvoltage event. The MOSFET junction
temperature must be kept below its absolute maximum
rating. For the overvoltage transient shown in Figure 10,
MOSFET Q1 conducts 0.55A (full load on all buck chan-
nels) while withstanding the voltage difference between
V
SUPPLY
(180V peak) and V
IN
(33V). This results in a peak
power of 81W. Since the overvoltage pulse in Figure 10
is roughly triangular, average power dissipation during
the transient event (about 400ms) is approximately half
the peak power. As such, the average power is given by:
P
AVG
(W) =
1
2
P
PEAK
(W) = 40.5W
In order to approximate the MOSFET junction temperature
rise from an overvoltage transient, one must determine
the MOSFET transient thermal response as well as the
MOSFET power dissipation. Fortunately
, most MOSFET
transient thermal response curves are provided by the
manufacturer (as shown in Figure 11). For a 400ms pulse
duration, the FQB34N20L MOSFET thermal response
Z
θJC
(t) is 0.65°C/W. The MOSFET junction temperature
rise is given by:
T
RISE
(°C) = Z
θJC
(t) • P
AVG
(W) = 26.3°C
Note that, by properly selecting MOSFET Q1, it is possible
to withstand even higher input voltage surges. Consult
manufacturer data sheets to ensure that the MOSFET
operates within its maximum safe operating area.
The application circuit start-up behavior is shown in
Figure 12. Resistor R2 pulls up on the gate of Q1, forcing
sour
ce connected V
IN
to follow approximately 3V below
V
SUPPLY
. Once V
IN
reaches the LT3514’s 3.2V minimum
start-up voltage, the on-chip boost converter immedi-
ately regulates the V
SKY
rail 4.85V above V
IN
. Diode D3
and resistor R3 bootstrap Q1’s gate voltage to the V
SKY
,
fully enhancing Q1. This connects V
IN
directly to V
SUPPLY
through Q1’s low resistance drain-source path. It should
be noted that, prior to V
SKY
being present, the minimum
input voltage is about 6.2V. However, with V
SKY
in regulation
and Q1 enhanced, the minimum run voltage drops to 3.2V,
permitting the LT3514 to maintain regulation through deep
input voltage dips Figure 13 shows all channels operating
down to the LT3514’s 3.2V minimum input voltage.
Z
θJC
(t), THERMAL RESPONSE (°C/W)
Z
θJC
(t) = 0.7°C/W MAX
DUTY FACTOR = D = t
1
/t
2
T
JM
– T
C
= P
DM
• Z
θJC
(t)
3514 F11
t
1
, SQUARE WAVE PULSE DURATION (s)
1010
–5
1
10
–3
10
–4
10
–3
0.01
0.1 1
0.01
0.1
D = 0.5
D = 0.2
D = 0.1
D = 0.05
D = 0.02
D = 0.01
SINGLE PULSE
P
DM
t
1
t
2
Figure 11. FQB34N20L Transient Thermal Response
Figure 12. Figure 9’s Start-Up Behavior
Figure 13. Figure 9’s Dropout Performance
20ms/DIV
3514 F12
SKY
2V/DIV
V
SUPPLY
2V/DIV
V
IN
2V/DIV
100ms/DIV
3514 F13
V
OUT3
1V/DIV
V
OUT1
1V/DIV
V
OUT4
1V/DIV
V
IN
1V/DIV
LT3514
23
3514fa
For more information www.linear.com/LT3514
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE24 (AA) TSSOP REV B 0910
0.09 – 0.20
(.0035 – .0079)
0° – 8°
0.25
REF
RECOMMENDED SOLDER PAD LAYOUT
0.50 – 0.75
(.020 – .030)
4.30 – 4.50*
(.169 – .177)
1 3 4
5
6
7
8 9 10 11 12
14 13
7.70 – 7.90*
(.303 – .311)
3.25
(.128)
2.74
(.108)
2021222324 19 18 17 16 15
1.20
(.047)
MAX
0.05 – 0.15
(.002 – .006)
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
2
2.74
(.108)
0.45 ±0.05
0.65 BSC
4.50 ±0.10
6.60 ±0.10
1.05 ±0.10
3.25
(.128)
MILLIMETERS
(INCHES)
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
SEE NOTE 4
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
6.40
(.252)
BSC
FE Package
24-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1771 Rev B)
Exposed Pad Variation AA
LT3514
24
3514fa
For more information www.linear.com/LT3514
PACKAGE DESCRIPTION
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
4.00 ±0.10
(2 SIDES)
2.50 REF
5.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
27 28
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
PIN 1 NOTCH
R = 0.20 OR 0.35
× 45° CHAMFER
0.25 ±0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UFD28) QFN 0506 REV B
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.50 REF
3.50 REF
4.10 ±0.05
5.50 ±0.05
2.65 ±0.05
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
2.65 ±0.10
3.65 ±0.10
3.65 ±0.05
UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev B)
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LT3514IUFD#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Triple Step-Down Switching Regulator with 100% Duty Cycle Operation
Lifecycle:
New from this manufacturer.
Delivery:
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