NCL30000
http://onsemi.com
17
Zero Current Detection (ZCD)
The signal controlling the ZCD function is taken from the
primary bias winding. Raising the ZCD pin above 1.4 V
arms the zero detection circuit. When the pin voltage
subsequently falls below 0.7 V, the controller issues the
command to turn the power switch back on. The current in
or out of the ZCD pin must be limited to 10 mA by an
external resistor. For this reference circuit a resistance of
47 kW provides the required voltage thresholds and limits
current to less than 10 mA.
Feedback Control
The secondary feedback signal is routed through an
optocoupler to the primary side NCL30000 controller. LED
current is measured with a 0.2 W resistor which for 350 mA
has a voltage drop of 70 mV.
The control loop must be designed to filter out the rectified
sine wave ripple component to provide an average feedback
level to the pulse width controller. In order to maintain high
power factor operation, the compensation components
around the error amplifier must be set well below 50/60 Hz.
The corner frequency typically falls between 10 and 40 Hz.
The low frequency response means the control loop will be
slow to compensate for rapidly changing situations. In
particular, the slow response can introduce overshoot at turn
on.
To compensate for the slow steady state loop this circuit
utilizes a second current control loop to minimize overshoot.
The second loop is set for higher than nominal operating
current with a very fast response loop. This error amp takes
control of the feedback loop until the main error amp is able
to respond. In this way the maximum current is limited to
safe established level.
The current set point of the fast control loop should be set
above the peak of the ripple current of normal operation. U4
is a 2.5 V reference which in conjunction with R26, R27, and
R28 establishes the nominal reference voltage of 70 mV
mentioned above but also the higher threshold for the fast
current loop. In this example, the average output current is
350 mA and the fast loop is set for a 500 mA level.
EMI Filter
The EMI filter attenuates the switching current drawn by
the power converter reducing the high frequency harmonics
to within conducted emissions limits. The filter must not
degrade the power factor by introducing a phase shift of the
current with the line-to-line or X capacitors. Low total
capacitance will minimize this effect. Balancing these
attributes is a performance tradeoff considering the wide
input voltage requirements.
A multi-stage filter consisting of 27 mH common mode
inductor and two 2.2 mH differential inductors working
with two 47 nF capacitors provides sufficient attenuation to
pass conducted emissions requirements. A 4.7 nF “Y1”
capacitor bypasses common mode currents created by the
power transformer.
The low input capacitance approach taken in this design
to meet high power factor has the added benefit of not
needing inrush current limiting.
Start-up Circuit and Primary Bias
Rapid start up is enhanced by the low current draw of the
NCL30000. Resistors connected from the rectified ac line to
the V
CC
circuit provide start up power. Some of the current
is needed for the control chip and bias network while the
remaining portion charges up a storage capacitor. When the
voltage on the capacitor reaches 12 V nominal, the internal
references and logic of the NCL30000 are turned on and the
part starts switching. The turn on comparator has hysteresis
(2.5 V nominal) to ensure sufficient time for the auxiliary
winding to start supplying current directly to the V
CC
capacitor. Resistor divider R9 (6.2 kW) and R15 (100 kW)
bias the MFP at the proper voltage to enable the NCL30000.
An optional thermal shutdown is implemented with
positive temperature coefficient (PTC) thermistor RT1. This
thermistor is placed close to the switching FET Q3 sensing
temperature stress related to load and surrounding
temperature. Situations causing excessive temperature will
cause RT1 to switch to a high impedance turning off the
NCL30000. When RT1 cools down, normal operation will
resume.
Transformer Design
Single stage high power factor flyback converters process
power in a sine-squared manner. To support the average
LED load current, the flyback converter must be capable of
processing 2 times the average output power. In this case,
the flyback transformer is designed to handle a peak power
of 42 W to power a 17.5 W LED load scaled for the
efficiency. The complete details of the transformer design
process are found in Application Note AND8451.
The NCL30000 is a variable frequency CrM controller
and as such the transformer determines the operating
frequency for a given set of input and output conditions. The
transformer turns ratio is controlled by maximum input and
output voltage and the ratings of the FET and output
rectifier. In this case, the turns ratio from primary to
secondary is set at 3.83.
Power switch on-time is set at the low line condition of
90 Vac or 126 V peak and maximum power of 17.5 W.
On-time will be 13.3 ms maximum. Primary inductance is
calculated from the minimum switching frequency and the
conditions listed above as 1.57 mH.
Peak primary current of 1.11 A is calculated from the
primary inductance, applied voltage, and on-time. Core flux
density occurs at the peak of the input rectified sine wave.
Primary turns are established from inductance, current,
maximum flux density and core geometry as 92 turns.
Primary turns, current, and maximum flux density set gap
size and is approximately 0.016 inches for this transformer.
The primary 92 turns divided by the previously calculated
ratio of 3.83 establishes secondary turns at 24. #26 triple
