74VCX16501MTD

© 2004 Fairchild Semiconductor Corporation DS500125 www.fairchildsemi.com
March 1998
Revised October 2004
74VCX16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX16501
Low Voltage 18-Bit Universal Bus Transceivers
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16501 is an 18-bit universal bus transceiver which
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA
), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the LOW-to-HIGH
transition of CLKAB. When OEAB is HIGH, the outputs are
active. When OEAB is LOW, the outputs are in a high-
impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA
, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA
is active
LOW).
The VCX16501 is designed for low voltage (1.4V to 3.6V)
V
CC
applications with I/O capability up to 3.6V.
The VCX16501 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
1.4V to 3.6V V
CC
supply operation
3.6V tolerant inputs and outputs
t
PD
(A to B, B to A)
2.9 ns max for 3.0V to 3.6V V
CC
Power-down high impedance inputs and outputs
Supports live insertion/withdrawal (Note 1)
Static Drive (I
OH
/I
OL
)
±24 mA @ 3.0V V
CC
Uses patented noise/EMI reduction circuitry
Latchup performance exceeds 300 mA
ESD performance:
Human body model
> 2000V
Machine model
>200V
Note 1: To ensure the high-impedance state during power up or power
down, OEBA
should be tied to V
CC
through a pull-up resistor and OEAB
should be tied to GND through a pull-down resistor; the minimum value of
the resistors is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
74VCX16501MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com 2
74VCX16501
Connection Diagram Pin Descriptions
Function Table
(Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 2: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA
,
LEBA and CLKBA. OEBA
is active LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Note 4: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
Pin Names Description
OEAB Output Enable Input for A to B Direction
(Active HIGH)
OEBA
Output Enable Input for B to A Direction
(Active LOW)
LEAB, LEBA Latch Enable Inputs
CLKAB,
CLKBA
Clock Inputs
A
1
A
18
Side A Inputs or 3-STATE Outputs
B
1
B
18
Side B Inputs or 3-STATE Outputs
Inputs Outputs
OEAB LEAB CLKAB
A
n
B
n
LXXX Z
HHXL L
HHXH H
HL
LL
HL
HH
HLHXB
0
(Note 3)
HLLXB
0
(Note 4)
3 www.fairchildsemi.com
74VCX16501
Logic Diagram

74VCX16501MTD

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
TXRX 18BIT UNIV BUS LV 56TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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