LTC3873-5
7
38735fb
OPERATION
Main Control Loop
The LTC3873-5 is a general purpose N-channel switching
DC/DC converter for boost, fl yback and SEPIC applications.
Its No R
SENSE
sensing technique improves effi ciency,
increases power density and reduces the cost of the
overall solution.
For circuit operation, please refer to the Functional Diagram
of the IC and the Typical Application on the front page.
During normal operation, the power MOSFET is turned
on when the oscillator sets the PWM latch and is turned
off when the current comparator resets the latch. The
divided-down output voltage is compared to an internal
1.2V reference by the error amplifi er, which outputs an
error signal at the I
TH
pin. The voltage on the I
TH
pin
sets the current comparator input threshold. When the
load current increases, a fall in the V
FB
voltage relative to
the reference voltage causes the I
TH
pin to rise, causing
the current comparator to trip at a higher peak inductor
current value. The average inductor current will therefore
rise until it equals the load current, thereby maintaining
output regulation.
The LTC3873-5 can be used either by sensing the voltage
drop across the power MOSFET or by connecting the SW
pin to a conventional sensing resistor in the source of the
power MOSFET. Sensing the voltage across the power
MOSFET maximizes converter effi ciency and minimizes the
component count; the maximum rating for this pin, 60V,
allows MOSFET sensing in a wide output voltage range.
Shunt Regulator
A built-in shunt regulator from the V
CC
pin to GND limits
the voltage on the V
CC
pin to approximately 9.3V as long as
the shunt regulator is not forced to sink more than 25mA.
The shunt regulator permits the use of a wide variety of
powering schemes that exceed the LTC3873-5’s absolute
maximum ratings. Further details on powering schemes
are described in the Application Information section.
Start-Up/Shutdown
The LTC3873-5 has two shutdown mechanisms to disable
and enable operation: an undervoltage lockout on the
V
CC
supply pin voltage and a threshold RUN/SS pin. The
LTC3873-5 transitions into and out of shutdown according
to the state diagram shown in Figure 3.
The undervoltage lockout (UVLO) mechanism prevents
the LTC3873-5 from trying to drive a MOSFET with in-
suffi cient V
GS
. The voltage at the V
CC
pin must exceed
Figure 1. SW Pin (Internal Sense Pin)
Connection for Maximum Effi ciency
Figure 2. SW Pin (Internal Sense Pin)
Connection for Sensing Resistor
Figure 3. Start-Up/Shut Down State Diagram
C
OUT
V
SW
V
OUT
V
IN
GND
L
D
+
NGATE
GND
V
CC
SW
38735 F01
LTC3873-5
C
OUT
V
SW
R
SENSE
R
SL
V
OUT
V
IN
GND
L
D
+
NGATE
GND
V
CC
SW
38735 F02
LTC3873-5
LTC3873-5
SHUT DOWN
V
RUN/SS
< V
SHDN
(NOMINALLY 0.7V)
38735 F03
V
IN
< V
TURNOFF
(NOMINALLY 2.9V)
V
RUN/SS
> V
SHDN
AND V
IN
> V
TURNON
(NOMINALLY 4.1V)
LTC3873-5
ENABLED
LTC3873-5
8
38735fb
OPERATION
V
TURNON
(nominally 4.1V) at least momentarily to enable
LTC3873-5 operation. The V
CC
voltage is then allowed to fall
to V
TURNOFF
(nominally 2.9V) before undervoltage lockout
disables the LTC3873-5. The RUN/SS pin can be driven
below V
SHDN
(nominally 0.7V) to force the LTC3873-5 into
shutdown. When the chip is off, the input supply current is
typically only 50A. Keep in mind that V
CC
should exceed
the gate threshold voltage of the switching MOSFET for
safe operation.
Soft-Start
Leave the RUN/SS pin open to use the internal 3.3ms
soft-start. During the internal soft-start, a voltage ramp
limits the V
ITH
. 3.3ms is required for I
TH
to ramp from
zero current level to full current level. The soft-start can
be lengthened by placing an external capacitor from the
RUN/SS pin to the GND. A 3A current will charge the
capacitor, pulling the RUN/SS pin above the shutdown
threshold and a 15µA pull-up current will continue to ramp
RUN/SS to limit V
ITH
during the start-up. When RUN/SS
is driven by an external logic, a minimum of 2.75V logic
is recommended to allow the maximum I
TH
range.
Light Load Operation
Under very light load current conditions, the I
TH
pin voltage
will be very close to 0.85V. As the load current decreases
further, an internal offset at the current comparator input
will assure that the current comparator remains tripped
(even at zero load current) and the regulator will start to
skip cycles in order to maintain regulation. This behavior
allows the regulator to maintain constant frequency down
to very light loads, resulting in low output ripple as well
as low audible noise and reduced RF interference while
providing high light load effi ciency.
Current Sense
During the switch on-time, the control circuit limits the
maximum voltage drop across the current sense com-
ponent to about 295mV, 110mV and 185mV at low duty
cycle with IPRG tied to V
IN
, GND or left fl oating respec-
tively. It is reduced with increasing duty cycle as shown
in Figure 4.
Figure 4. Maximum SENSE Threshold Voltage vs Duty Cycle
DUTY CYCLE (%)
1
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
50
100
150
200
250
300
20 40 60 80
3873-5 F04
100
IPRG = HIGH
IPRG = FLOAT
IPRG = LOW
LTC3873-5
9
38735fb
V
CC
Bias Power
The V
CC
pin must be bypassed to the GND pin with a
minimum 10F ceramic or tantalum capacitor located
immediately adjacent to the two pins. Proper supply by-
passing is necessary to supply the high transient currents
required by the MOSFET gate driver.
For maximum fl exibility, the LTC3873-5 is designed so
that it can be operated from voltages well beyond the
LTC3873-5’s absolute maximum ratings. In the simplest
case, the LTC3873-5 can be powered with a resistor con-
nected between the input voltage and V
CC
. The built-in shunt
regulator limits the voltage on the V
CC
pin to around 9.3V
as long as the shunt regulator is not forced to sink more
than 25mA. This powering scheme has the drawback that
the power loss in the resistor reduces converter effi ciency
and the 25mA shunt regulator maximum may limit the
maximum-minimum range of input voltage.
The circuit in Figure 5 shows a second way to power the
LTC3873-5. An external series pre-regulator consisting of
series pass transistor Q1, zener diode D1 and bias resis-
tor R
B
brings V
CC
to at least 7.6V nominal, well above the
undervoltage lockout threshold.
resistor (R
SL
) connecting the SW pin to the current sense
resistor (R
SENSE
) thus develops a ramping voltage drop.
From the perspective of the SW pin, this ramping voltage
adds to the voltage across the sense resistor, effectively
reducing the current comparator threshold in proportion
to duty cycle. The amount of reduction in the current
comparator threshold (ΔV
SENSE
) can be calculated using
the following equation:
ΔV
Duty Cycle
AR
SENSE SLOPE
=
–%
%
6
80
20μ
Note the external programmable slope compensation is
only needed when the internal slope compensation is not
suffi cient. In some applications R
SL
can be shorted. For
the LTC3873-5, when the R
DS(ON)
sensing technique is
used, the ringing on the SW pin disrupts the tiny slope
compensation current out of the pin. It is not recommended
to add external slope compensation in this case.
Output Voltage Programming
The output voltage is set by a resistor divider according
to the following formula:
VV
R
R
O
=+
12 1
2
1
.•
The external resistor divider is connected to the output
as shown in Figure 4, allowing remote voltage sensing.
Choose resistance values for R1 and R2 to be as large as
possible in order to minimize any effi ciency loss due to
the static current drawn from V
OUT
, but just small enough
so that when V
OUT
is in regulation, the error caused by
the nonzero input current to the V
FB
pin is less than 1%.
A good rule of thumb is to choose R1 to be 24k or less.
Transformer Design Considerations
Transformer specifi cation and design is perhaps the most
critical part of applying the LTC3873-5 successfully. In
addition to the usual list of caveats dealing with high fre-
quency power transformer design, the following should
prove useful.
APPLICATIONS INFORMATION
Figure 5. External Pre-Regulator for V
CC
Bias Power
Slope Compensation
The LTC3873-5 has built-in internal slope compensation
to stabilize the control loop against sub-harmonic oscilla-
tion. It also provides the ability to externally increase slope
compensation by injecting a ramping current out of its
SW pin into an external slope compensation resistor (R
SL
in Figure 2). This current ramp starts at zero right after
the NGATE pin has been high. The current rises linearly
towards a peak of 20µA at the maximum duty cycle of
80%, shutting off once the NGATE pin goes low. A series
LTC3873-5
V
CC
38735 F05
Q1
R
B
V
IN
C
VCC
0.1µF
D1
8.2V
GND

LTC3873ETS8-5#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators No Rsense Constant Frequency Current Mode Boost/Flyback/SEPIC DC/DC Controller
Lifecycle:
New from this manufacturer.
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