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74LCX841MSA

P1-P3P4-P6P7-P8
© 2001 Fairchild Semiconductor Corporation DS012575 www.fairchildsemi.com
October 1995
Revised March 2001
74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX841
Low Voltage 10-Bit Transparent Latch
with 5V Tolerant Inputs and Outputs
General Description
The LCX841 consists of ten latches with 3-STATE outputs
for bus organized system applications. The device is
designed for low voltage (2.5V or 3.3V) V
CC
applications
with capability of interfacing to a 5V signal environment.
The LCX841 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
■ 5V tolerant inputs and outputs
■ 2.3V
− 3.6V V
CC
specifications provided
■ 8.0 ns t
PD
max (V
CC
= 3.3V), 10 µA I
CC
max
■ Power-down high impedance inputs and outputs
■ Supports live insertion/withdrawal (Note 1)
■
±24 mA output drive (V
CC
= 3.0V)
■ Implements patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 500 mA
■ ESD performance:
Human Body Model
> 2000V
Machine Model
> 200V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74LCX841WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74LCX841MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74LCX841MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
www.fairchildsemi.com 2
74LCX841
Pin Descriptions Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impendance
NC = No Change
Functional Description
The LCX841 consists of ten D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion.
On the LE HIGH-to-LOW transition, the data that meets the
setup and hold time is latched. Data appears on the bus
when the Output Enable (OE
) is LOW. When OE is HIGH
the bus output is in the high impedance state.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
D
0
–D
9
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0
–O
9
3-STATE Latch Outputs
Inputs Internal Output
Function
OE
LE D Q O
X X X X Z High Z
H H L L Z High Z
HHH H Z High Z
H L X NC Z Latched
L H L L L Transparent
L H H H H Transparent
L L X NC NC Latched
3 www.fairchildsemi.com
74LCX841
Absolute Maximum Ratings(Note 2)
Recommended Operating Conditions (Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recom-
mended Operating Conditions” table will define the conditions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol Parameter Value Conditions Units
V
CC
Supply Voltage −0.5 to +7.0 V
V
I
DC Input Voltage −0.5 to +7.0 V
V
O
DC Output Voltage −0.5 to +7.0 Output in 3-STATE
V
−0.5 to V
CC
+ 0.5 Output in HIGH or LOW State (Note 3)
I
IK
DC Input Diode Current −50 V
I
< GND mA
I
OK
DC Output Diode Current −50 V
O
< GND
mA
+50 V
O
> V
CC
I
O
DC Output Source/Sink Current ±50 mA
I
CC
DC Supply Current per Supply Pin ±100 mA
I
GND
DC Ground Current per Ground Pin ±100 mA
T
STG
Storage Temperature −65 to +150 °C
Symbol Parameter Min Max Units
V
CC
Supply Voltage Operating 2.0 3.6
V
Data Retention 1.5 3.6
V
I
Input Voltage 05.5V
V
O
Output Voltage HIGH or LOW State 0 V
CC
V
3-STATE 0 5.5
I
OH
/I
OL
Output Current V
CC
= 3.0V − 3.6V ±24
mAV
CC
= 2.7V − 3.0V ±12
V
CC
= 2.3V − 2.7V ±8
T
A
Free-Air Operating Temperature −40 85 °C
∆t/∆V Input Edge Rate, V
IN
= 0.8V − 2.0V, V
CC
= 3.0V 0 10 ns/V
Symbol Parameter Conditions
V
CC
T
A
= −40°C to +85°C
Units
(V) Min Max
V
IH
HIGH Level Input Voltage 2.3 − 2.7 1.7
V
2.7 − 3.6 2.0
V
IL
LOW Level Input Voltage 2.3 − 2.7 0.7
V
2.7 − 3.6 0.8
V
OH
HIGH Level Output Voltage I
OH
= −100 µA2.3 − 3.6 V
CC
− 0.2
V
I
OH
= −8 mA 2.3 1.8
I
OH
= −12 mA 2.7 2.2
I
OH
= −18 mA 3.0 2.4
I
OH
= −24 mA 3.0 2.2
V
OL
LOW Level Output Voltage I
OH
= 100 µA2.3 − 3.6 0.2
V
I
OH
= 8 mA 2.3 0.6
I
OL
= 12 mA 2.7 0.4
I
OL
= 16 mA 3.0 0.4
I
OL
= 24 mA 3.0 0.55
I
I
Input Leakage Current 0 ≤ V
I
≤ 5.5V 2.3 − 3.6 ±5.0 µA
I
OZ
3-STATE Output Leakage 0 ≤ V
O
≤ 5.5V
2.3 − 3.6 ±5.0 µA
V
I
= V
IH
or V
IL
I
OFF
Power-Off Leakage Current V
I
or V
O
= 5.5V 0 10 µA
P1-P3P4-P6P7-P8

74LCX841MSA

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Description:
ICLATCH TRANSP 10BIT LV 24SSOP
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