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MC74VHCT00ADR2

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 6
1 Publication Order Number:
MC74VHCT00A/D
MC74VHCT00A
Quad 2-Input NAND Gate
The MC74VHCT00A is an advanced high speed CMOS 2−input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHCT00A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when V
CC
= 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
• High Speed: t
PD
= 5.0 ns (Typ) at V
CC
= 5 V
• Low Power Dissipation: I
CC
= 2 μA (Max) at T
A
= 25°C
• TTL−Compatible Inputs: V
IL
= 0.8 V; V
IH
= 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Designed for 3.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: 48 FETs or 12 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
MARKING DIAGRAMS
14
1
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
VHCT00AG
AWLYWW
1
14
VHCT
00A
ALYWG
G
1
14
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the
dimensions section on page 6 of this data sheet.
http://onsemi.com
MC74VHCT00A
http://onsemi.com
2
Figure 1. Pin Assignment
(Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
Figure 2. Logic Diagram
3
Y1
1
A1
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
H
H
H
L
Y
Figure 3. IEC LOGIC DIAGRAM
3
A1
B1
&
6
8
11
1
2
A2
B2
4
5
A3
B3
9
10
A4
B4
12
13
Y1
Y2
Y3
Y4
PIN ASSIGNMENT
1
2
3 OUT Y1
IN A1
IN B1
4
5 IN B2
IN A2
6
7
8 OUT Y3
OUT Y2
GND
9
IN B3
IN A3
10
11
12 IN A4
OUT Y4
13
14 V
CC
IN B4
MC74VHCT00A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Characteristics Value Unit
V
CC
DC Supply Voltage −0.5 to +7.0 V
V
IN
DC Input Voltage −0.5 to +7.0 V
V
OUT
DC Output Voltage V
CC
= 0
High or Low State
−0.5 to 7.0
−0.5 to V
CC
+ 0.5
V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current V
OUT
< GND; V
OUT
> V
CC
+20 mA
I
OUT
DC Output Current, per Pin +25 mA
I
CC
DC Supply Current, V
CC
and GND +50 mA
P
D
Power Dissipation in Still Air, SOIC Package (Note 1)
TSSOP Package (Note 1)
500
450
mW
T
L
Lead temperature, 1 mm from case for 10 s 260 °C
T
stg
Storage temperature −65 to +150 °C
V
ESD
ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
> 3000
V
I
Latch−Up
Latch−Up Performance Above V
CC
and Below GND at 125°C
(Note 5)
±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are
exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
1. Derating − SOIC Package: –7 mW/_C from 65_ to 125_C
− TSSOP Package: −6.1 mW/_C from 65_ to 125_C
2. Tested to EIA/JESD22−A114−A
3. Tested to EIA/JESD22−A115−A
4. Tested to JESD22−C101−A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol Characteristics Min Max Unit
V
CC
DC Supply Voltage 3.0 5.5 V
V
IN
DC Input Voltage 0.0 5.5 V
V
OUT
DC Output Voltage VCC = 0
High or Low State
0.0
0.0
5.5
V
CC
V
T
A
Operating Temperature Range −55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3 V ± 0.3 V
V
CC
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
This device contains
protection circuitry to guard
against damage due to high
static voltages or electric
fields. However, pre-
cautions must be taken to
avoid applications of any
voltage higher than maxi-
mum rated voltages to this
high−impedance circuit. For
proper operation, V
in
and
V
out
should be constrained
to the range GND v (V
in
or
V
out
) v V
CC
.
Unused inputs must al-
ways be tied to an appropri-
ate logic voltage level (e.g.,
either GND or V
CC
). Un-
used outputs must be left
open.
P1-P3P4-P6P7-P8

MC74VHCT00ADR2

Mfr. #:
Buy MC74VHCT00ADR2
Manufacturer:
ON Semiconductor
Description:
Logic Gates 3-5.5V Quad 2-Input
Lifecycle:
New from this manufacturer.
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