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AD8067ARTZ-R2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
AD8067 Data Sheet
Rev. B | Page 14 of 24
For inverting voltage gain applications, the source impedance of
the input signal must be considered because it sets the application’s
noise gain as well as the apparent closed-loop gain. The basic
frequency equation for inverting applications is
SG
F
SG
RRR
RR
GBPequencyp –3 dB FrClosed-Loo
)(
SG
F
RR
R
GainDC
–
where GBP is the gain bandwidth product of the amplifier, and
R
S
is the signal source resistance.
SG
SG
F
RR
RRR
GainNoiseionConfiguratInverting
It is important that the noise gain for inverting applications be
kept above 6 for stability reasons. If the signal source driving
the inverter is another amplifier, take care that the driving
amplifier shows low output impedance through the frequency
span of the expected closed-loop bandwidth of the AD8067.
RESISTOR SELECTION FOR WIDEBAND OPERATION
Voltage feedback amplifiers can use a wide range of resistor
values to set their gain. Proper design of the application’s
feedback network requires consideration of the following issues:
Poles formed by the amplifier’s input capacitances with the
resistances seen at the amplifier’s input terminals
Effects of mismatched source impedances
Resistor value impact on the application’s output
voltage noise
Amplifier loading effects
The AD8067 has common-mode input capacitances (C
M
) of
1.5 pF and a differential input capacitance (C
D
) of 2.5 pF. This is
illustrated in Figure 43. The source impedance driving the
positive input of a noninverting buffer forms a pole primarily
with the amplifier’s common-mode input capacitance as well as
any parasitic capacitance due to the board layout (C
PAR
). This
limits the obtainable bandwidth. For G = +10 buffers, this
bandwidth limit becomes apparent for source impedances >1 kΩ.
V
I
R
S
SIGNAL SOURCE
–
+
–
+
V
OU
T
–
+
C
PAR
C
PAR
R
G
C
D
C
M
C
M
R
F
Figure 43. Input and Board Capacitances
There is a pole in the feedback loop response formed by
the source impedance seen by the amplifier’s negative input
(R
G
R
F
) and the sum of the amplifier’s differential input
capacitance, common-mode input capacitance, and any board
parasitic capacitance. This decreases the loop phase margin and
can cause stability problems, that is, unacceptable peaking and
ringing in the response. To avoid this problem, it is recommended
that the resistance at the AD8067’s negative input be kept below
200 Ω for all wideband voltage gain applications.
Matching the impedances at the inputs of the AD8067 is also
recommended for wideband voltage gain applications. This
minimizes nonlinear common-mode capacitive effects that can
significantly degrade settling time and distortion performance.
The AD8067 has a low input voltage noise of 6.6 nV/
Hz.
Source resistances greater than 500 Ω at either input terminal
notably increases the apparent referred-to-input (RTI) voltage
noise of the application.
The amplifier must supply output current to its feedback
network, as well as to the identified load. For instance, the
load resistance presented to the amplifier in Figure 40 is
R
LOAD
 (R
F
+ R
G
). For an R
LOAD
of 100 Ω, R
F
of 1 kΩ, and R
G
of
100 Ω, the amplifier is driving a total load resistance of about
92 Ω. This becomes more of an issue as R
F
decreases. The
AD8067 is rated to provide 30 mA of low distortion output
current. Heavy output drive requirements also increase the
part’s power dissipation and should be taken into account.
Data Sheet AD8067
Rev. B | Page 15 of 24
DC ERROR CALCULATIONS
Figure 44 illustrates the primary dc errors associated with a
voltage feedback amplifier. For both inverting and noninverting
configurations:
+
=
G
F
G
OSOS
R
RR
VVtodueErrorVoltageOutput
FB–
G
G
F
S
BB
RI
R
RR
RIItodueErrorVoltageOutput ×
+
×=
+
–
Total error is the sum of the two.
DC common-mode and power supply effects can be added by
modeling the total V
OS
with the expression:
CMR
V
PSR
V
nomVtotV
CMS
OSOS
ΔΔ
)()( ++=
where:
V
OS
(nom) is the offset voltage specified at nominal conditions
(1 mV max).
∆V
S
is the change in power supply voltage from nominal
conditions.
PSR is power supply rejection (90 dB minimum).
∆V
CM
is the change in common-mode voltage from nominal test
conditions.
CMR is the common-mode rejection (85 dB minimum for the
AD8067).
V
I
R
S
R
G
I
B
+
I
B
–
–
+
V
OUT
–
+
–
+
+V
OS
–
R
F
Figure 44. Op Amp DC Error Sources
INPUT AND OUTPUT OVERLOAD BEHAVIOR
A simplified schematic of the AD8067 input stage is shown in
Figure 45. This shows the cascoded N-channel JFET input pair,
the ESD and other protection diodes, and the auxiliary NPN
input stage that eliminates phase inversion behavior.
When the common-mode input voltage to the amplifier is
driven to within approximately 3 V of the positive power
supply, the input JFET’s bias current turns off, and the bias of
the NPN pair turns on, taking over control of the amplifier. The
NPN differential pair now sets the amplifier’s offset, and the
input bias current is now in the range of several tens of
microamps. This behavior is illustrated in Figure 25 and Figure 26.
Normal operation resumes when the common-mode voltage
goes below the 3 V from the positive supply threshold.
The output transistors have circuitry included to limit the
extent of their saturation when the output is overdriven. This
improves output recovery time. A plot of the output recovery
time for the AD8067 used as a G = +10 buffer is shown in
Figure 17.
V
BIAS
V
CC
V
EE
V
EE
V
CC
V
P
V
N
SWITCH
CONTROL
V
EE
V
CC
TO REST OF AMP
V
THRESHOLD
Figure 45. Simplified Input Schematic
AD8067 Data Sheet
Rev. B | Page 16 of 24
INPUT PROTECTION
The inputs of the AD8067 are protected with back-to-back
diodes between the input terminals as well as ESD diodes to
either power supply. The result is an input stage with picoamp
level input currents that can withstand 2 kV ESD events
(human body model) with no degradation.
Excessive power dissipation through the protection devices
destroys or degrades the performance of the amplifier.
Differential voltages greater than 0.7 V result in an input
current of approximately (| V
+
– V
−
| − 0.7 V)/(R
I
+ R
G
)),
where R
I
and R
G
are the resistors (see Figure 46). For input
voltages beyond the positive supply, the input current is about
(V
I
– V
CC
– 0.7 V)/R
I
. For input voltages beyond the negative
supply, the input current is about (V
I
– V
EE
+ 0.7 V)/R
I
. For any
of these conditions, R
I
should be sized to limit the resulting
input current to 50 mA or less.
V
I
R
I
> (V
I
– V
EE
+ 0.7V)/50mA
R
I
> (V
I
– V
CC
– 0.7V)/50mA
FOR V
I
BEYOND
SUPPLY VOLTAGES
V
OUT
–
+
R
G
R
F
R
I
–
+
AD8067
R
I
> ( |V+ – V– | –0.7V)/50mA
FOR LARGE |V
+
– V– |
Figure 46. Current Limiting Resistor
CAPACITIVE LOAD DRIVE
Capacitive load introduces a pole in the amplifier loop response
due to the finite output impedance of the amplifier. This can
cause excessive peaking and ringing in the response. The
AD8067 with a gain of +10 handles up to a 30 pF capacitive
load without an excessive amount of peaking (see Figure 8). If
greater capacitive load drive is required, consider inserting a
small resistor in series with the load (24.9 Ω is a good value to
start with). Capacitive load drive capability also increases as the
gain of the amplifier increases.
LAYOUT, GROUNDING, AND BYPASSING
CONSIDERATIONS
Layout
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 10× the input bias
current of the amplifier. Poor PCB layout, contamination, and
the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and the board surface be free of contaminants
to fully take advantage of the AD8067’s low input bias currents.
To significantly reduce leakage paths, a guard-ring/shield
around the inputs should be used. The guard-ring circles the
input pins and is driven to the same potential as the input
signal, thereby reducing the potential difference between pins.
For the guard ring to be completely effective, it must be driven
by a relatively low impedance source and should completely
surround the input leads on all sides, above, and below, using a
multilayer board (see Figure 47). The SOT-23-5 package
presents a challenge in keeping the leakage paths to a minimum.
The pin spacing is very tight, so extra care must be used when
constructing the guard ring (see Figure 48 for recommended
guard-ring construction).
NONINVERTING
GUARD RING
INVERTING
GUARD RING
Figure 47. Guard-Ring Configurations
+V
–IN
+IN
–V
V
OUT
AD8067
NONINVERTING
+V
–IN
+IN
–V
V
OUT
AD8067
INVERTING
Figure 48. Guard-Ring Layout SOT-23-5
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

AD8067ARTZ-R2

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