4
Commercial Temperature Range
IDT728981 Time Slot Interchange
Digital Switch 128 x 128
SOFTWARE CONTROL
If the A5 address line input is LOW then the IDT728981 Internal Control
Register is addressed. If A5 input line is high, then the remaining address input
lines are used to select the 32 possible channels per input or output stream. The
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT728981 Data and
Connection memories. The IDT728981 memory mapping is illustrated in Table
2 and Figure 3.
The data in the control register (Table 3) consists of Memory Select and
Stream Address bits, Split Memory and Processor Mode bits. In Split Memory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory as specified by the Memory Select Bits (Bits 4
and 3 of the Control Register). The Memory Select bits allow the Connection
Memory HIGH or LOW or the Data Memory to be chosen, and the Stream
Address bits define internal memory subsections corresponding to input or
output streams.
The Processor Enable bit (bit 6) places EVERY output channel on every
output stream in Processor mode; i.e., the contents of the Connection Memory
LOW (CML, see Table 5)) are output on the TX output streams once every frame
unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT728981 behaves
as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection
Memory High (CMH) locations were set to HIGH, regardless of the actual value.
Connection Memory High
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1 Channel 2 Channel 31
Channel 0 Channel 1
100001 100010 111111
Data Memory
0 0 0
0 1 1
1
0 2
1 1 3
0 1
1 0
1 1
100000
Channel 2 Channel 31
Connection Memory Low
Stream
Control Register CR
b
7
External Address Bits A5-A0
5703 drw07
The Control Register is only accessed when A5=0.
All other address bits have no effect when A5=0.
When A5 =1, only 32 bytes are randomly accessable
via A0-A4 at any one instant. Which 32 bytes are
accessed is determined by the state of CRb0 -CRb4.
The 32 bytes correlate to 32 channel of one ST-BUS
®
stream.
CR
b
6CR
b
5CR
b
4CR
b
3CR
b
2CR
b
1CR
b
0
CR
b
1CR
b
0
CR
b
4CR
b
3
Figure 3. Address Mapping
If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
the CML define the source information (stream and channel) of the time slot that
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)
or disables (if LOW) the output stream and channel.
INITIALIZATION OF THE IDT728981
On initialization or power up, the contents of the Connection Memory High
can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on
power up to keep all outputs in the high impedance condition until the contents
of the CMH are programmed.
During the microprocessor initialization routine, the microprocessor should
program the desired active paths through the matrices, and put all other channels
into the high impedance state. Care should be taken that no two connected TX
outputs drive the bus simultaneously. With the CMH setup, the microprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
