XLL535A00.000000I Datasheet XLL535100.000000I, XLL535125.000000I, XLL536025.000000I | P4-P6

FXO-LC53 Series

Page 4 of 15

Note1

An optional PIN # 2 as Enable / Disable is available – see Model Selection Guide (page 2)

Output Wave Characteristics

Parameters

Symbol

Condition

Maximum Value

(unless otherwise noted)

Differential Output Voltage V

OD

0.75 MHz to 1.35 GHz 0.6V Typ.

Output Offset Voltage V

OS

Volts DC 1.3V Typ.

Output Symmetry (See Drawing Below) @ 50% V

P-P

Level 45% ~ 55%

Output Enable

(PIN # 1)

Voltage

Note1

V

IH

> 70% V

DD

Output Disable

(PIN # 1)

Voltage

Note1

V

IL

< 30% V

DD

Cycle Rise Time (See Drawing Below) T

R

20%~80% 400 pS

Cycle Fall Time

(See Drawing Below) T

F

80%~20% 400 pS

Ideally, Symmetry should be 50/50 for 1/2 period -- Other expressions are 45/55 or 55/45

OUTPUT 1

OUTPUT 2

50% V

P-P

1/2 Period

Period

Oscillator Symmetry

Rise Time / Fall Time Measurements

OUTPUT 1

20% to 80%

OUTPUT 2

T

R

T

F

1.30V Typ.

50% V

P-P

0.6V Typ.

P-P

FXO-LC53 Series

Page 5 of 15

Jitter is frequency dependent. Below are typical values at select frequencies.

Phase Jitter is integrated from HP3048 Phase Noise Measurement System; measured directly into 50 ohm input; V

DD

= 3.3V.

TIE

was measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software; V

DD

= 3.3V.

Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)

Rj and Dj, measured on LeCroy LC684 Digital Storage Scope, directly into 50 ohm input, with Amherst M1 software.

Per MJSQ spec (Methodologies for Jitter and Signal Quality specifications)

LVDS Phase Jitter & Time Interval Error (TIE)

Frequency

Phase Jitter

(12kHz to 20MHz)

T I E

(Sigma of Jitter Distribution)

Units

62.5 MHz 0.77 3.0 pS RMS

156.25 MHz 1.19 3.6 pS RMS

212.5 MHz 0.89 3.9 pS RMS

622.08MHz

0.99

3.2

pS RMS

LVDS Random & Deterministic Jitter Composition

Frequency

Random (Rj)

(pS RMS)

Deterministic (Dj)

(pS P-P)

Total Jitter (Tj)

(14 x Rj) + Dj

62.5 MHz 1.3 7.0 24.9 pS

156.25 MHz 1.3 5.8 23.6 pS

212.5 MHz 0.9 6.7 18.7 pS

622.08 MHz

1.1

5.3

20.7 pS

Phase Noise

Offset Frequenc

y

(

10Hz to 40MHz

)

(dBc / Hz) vs. offset frequency

Phase Noise Graph

1k

-110dBc

-120dBc

-130dBc

-150dBc

-140dBc

-160dBc

10 100

-100dBc

-60dBc

-80dBc

-90dBc

-70dBc

-40dBc

-50dBc

-30dBc

-20dBc

-10dBc

0 dBc

1M10k 100k

FOUR frequencies matching

10M 40M

62.5 MHz

212.5 MHz

622.08 MHz

62.5 MHz

622.08 MHz

212.5 MHz

156.25MHz

Data Collected using HP 3048A

the below jitter measurements

FXO-LC53 Series

Page 6 of 15

NOTE: XPRESSO LVDS XOs are designed to

fit on Industry Standard, 6 pad layouts

Pin Description and Recommended Circuit

Pin #

Name

Type

Function

1

E / D

1

Logic Enable / Disable Control of Output (0 = Disabled)

2

NC

No Connection – Leave OPEN

3 GND Ground Electrical Ground for V

DD

4 Output Output LVDS Oscillator Output

5 Output 2 Output Complimentary LVDS Output

6

V

DD

2

Power Power Supply Source Voltage

NOTES:

1

Includes pull-up resistor to V

DD

to provide output when the pin (1) is No Connect.

2

Installation should include a 0.01µF bypass capacitor placed between V

DD

(Pin 6) and GND (Pin 3) to minimize power supply line noise.

E / D V

DD

NC Output 2

GND Output

Terminations as viewed from the Top

Enable / Disable Control

Pin # 1 (state) Output (Pin # 4, Pin # 5)

OPEN

(No Connection)

ACTIVE Output

“1” Level V

IH

> 70% V

DD

ACTIVE Output

“0” Level V

IL

< 30% V

DD

High Impedance

3

1

4

6

Soldering Reflow Profile (2 times Maximum at 260°C for 10 seconds MAX)

25°C

160°C

180°C

225°C

260°C

10 Seconds Max

within 5°C of 260°C peak

Ramp Down

Not to exceed 6°C/s

Ramp-Up

3°C/s Max

p

t

120 ± 20 Seconds

In Pre-heating Area

Above 225°C Reflow Area

50±10 Seconds

400 Seconds MAX from +25°C to 260°C peak

2

5

# 5# 2N C

GND

# 3 # 4

E/D # 1 # 6

0.01 F

V

DD

OUTPUT 2

100

OUTPUT

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XLL535A00.000000I

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