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74LVCH16374ADGG:11

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
74LVC_LVCH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 16 January 2013 9 of 20
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
[1] All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
=25C.
[2] The bus hold circuit is switched off when V
I
>V
CC
allowing 5.5 V on the input pin.
[3] Valid for data inputs (74LVCH16374A) only; control inputs do not have a bus hold circuit.
[4] The specified sustaining current at the data inputs holds the input below the specified V
I
level.
[5] The specified overdrive current at the data input forces the data input to the opposite logic input state.
10. Dynamic characteristics
I
BHHO
bus hold
HIGH
overdrive
current
V
CC
= 1.95 V
[3][5]
200 - - 200 - A
V
CC
= 2.7 V 300 - - 300 - A
V
CC
= 3.6 V 500 - - 500 - A
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10
.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
t
pd
propagation
delay
nCP to nQn; see Figure 7
[2]
V
CC
= 1.2 V - 14 - - - ns
V
CC
= 1.65 V to 1.95 V 2.1 6.9 13.5 2.1 15.6 ns
V
CC
= 2.3 V to 2.7 V 1.5 3.7 6.7 1.5 7.7 ns
V
CC
= 2.7 V 1.5 3.4 6.0 1.5 7.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.1 5.4 1.5 7.0 ns
t
en
enable time nOE to nQn; see Figure 9
[2]
V
CC
= 1.2 V - 20 - - - ns
V
CC
= 1.65 V to 1.95 V 1.5 5.9 13.1 1.5 15.1 ns
V
CC
= 2.3 V to 2.7 V 1.5 3.4 6.9 1.5 8.0 ns
V
CC
= 2.7 V 1.5 3.6 6.0 1.5 7.5 ns
V
CC
= 3.0 V to 3.6 V 1.0 2.7 5.2 1.0 6.5 ns
t
dis
disable time nOE to nQn; see Figure 7
[2]
V
CC
= 1.2 V - 12 - - - ns
V
CC
= 1.65 V to 1.95 V 2.8 4.6 9.1 2.8 10.5 ns
V
CC
= 2.3 V to 2.7 V 1.0 2.5 4.9 1.0 5.7 ns
V
CC
= 2.7 V 1.5 3.4 5.1 1.5 6.5 ns
V
CC
= 3.0 V to 3.6 V 1.5 3.1 4.9 1.5 6.5 ns
t
W
pulse width nCP HIGH; see Figure 7
V
CC
= 1.65 V to 1.95 V 5.0 - - 5.0 - ns
V
CC
= 2.3 V to 2.7 V 4.0 - - 4.0 - ns
V
CC
= 2.7 V 3.0 - - 3.0 - ns
V
CC
= 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns
74LVC_LVCH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 16 January 2013 10 of 20
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
[1] Typical values are measured at T
amb
=25C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
(C
L
V
CC
2
f
o
) = sum of the outputs
t
su
set-up time nDn to nCP; see Figure 8
V
CC
= 1.65 V to 1.95 V 4.0 - - 4.0 - ns
V
CC
= 2.3 V to 2.7 V 3.0 - - 3.0 - ns
V
CC
= 2.7 V 1.9 - - 1.9 - ns
V
CC
= 3.0 V to 3.6 V 1.9 0.3 - 1.9 - ns
t
h
hold time nDn to nCP; see Figure 8
V
CC
= 1.65 V to 1.95 V 3.0 - - 3.0 - ns
V
CC
= 2.3 V to 2.7 V 2.5 - - 2.5 - ns
V
CC
= 2.7 V 1.1 - - 1.1 - ns
V
CC
= 3.0 V to 3.6 V +1.5 0.3 - 1.5 - ns
f
max
maximum
frequency
see Figure 7
V
CC
= 1.65 V to 1.95 V 100 - - 80 - ns
V
CC
= 2.3 V to 2.7 V 125 - - 100 - ns
V
CC
= 2.7 V 150 - - 120 - MHz
V
CC
= 3.0 V to 3.6 V 150 300 - 120 - MHz
t
sk(o)
output skew
time
V
CC
= 3.0 V to 3.6 V
[3]
- - 1.0 - 1.5 ns
C
PD
power
dissipation
capacitance
per input; V
I
=GNDtoV
CC
[4]
V
CC
= 1.65 V to 1.95 V - 14.1 - - - pF
V
CC
= 2.3 V to 2.7 V - 16.4 - - - pF
V
CC
= 3.0 V to 3.6 V - 18.5 - - - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
74LVC_LVCH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 16 January 2013 11 of 20
NXP Semiconductors
74LVC16374A; 74LVCH16374A
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
11. Waveforms
Measurement points are given in Table 8.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 7. Clock (nCP) to output (nQn) propagation delays, clock pulse width, and the maximum frequency
001aaa256
nCP input
nQn
output
t
PHL
t
PLH
t
W
V
OH
V
I
GND
V
OL
V
M
V
M
V
M
1/f
max
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable performance.
V
OL
and V
OH
are the typical output voltage levels that occur with the output load.
Fig 8. Data set-up and hold times for the nDn input to the nCP input
001aaa257
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
nQn output
nCP input
nDn input
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74LVCH16374ADGG:11

Mfr. #:
Buy 74LVCH16374ADGG:11
Manufacturer:
Nexperia
Description:
Flip Flops IC 16BIT EDGE TRIG D FF
Lifecycle:
New from this manufacturer.
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