Data Sheet ADP197
Rev. C | Page 9 of 13
3
2
1
CH1 AMPL
2.12A
CH1 1A
CH3 2V
CH2 2V M1.00ms A CH3 1.28V
T 10.00%
B
W
B
W
B
W
09298-015
I
LOAD
V
OUT
V
EN
Figure 23. Typical Turn-On Time and Inrush Current, V
IN
= 5.5 V,
2 A Load, C
OUT
= 100 μF
0.0001
0.001
0.01
0.1
1
10
–40 –20 0 20 40 60 80 100
I
OUT
SHUTDOWN CURRENT
(
µA)
TEMPERATUREC)
1.8V
1.9V
2.5V
3.0V
3.4V
3.8V
4.2V
4.6V
5.0V
5.5V
09298-022
Figure 24. I
OUT
Shutdown Current vs. Temperature, V
OUT
= 0 V, Different Input
Voltages (V
IN
)
ADP197 Data Sheet
Rev. C | Page 10 of 13
THEORY OF OPERATION
GND
EN
VIN
VOUT
ADP197
ADP197-02
ONLY
CHARGE PUMP
AND SLEW RATE
CONTROL
09298-023
OVERTEMPERATURE
PROTECTION
Figure 25. Functional Block Diagram
The ADP197 is a high-side NMOS load switch, controlled by an
internal charge pump. The ADP197 is designed to operate with
power supply voltages between 1.8 V and 5.5 V.
An internal charge pump biases the NMOS switch to achieve a
relatively constant, ultralow on resistance of 12 mΩ across the
entire input voltage range. The use of the internal charge pump
also allows for controlled turn-on times. Turning the NMOS
switch on and off is controlled by the enable input pin (EN), which
is capable of interfacing directly with 1.8 V logic signals.
The ADP197 is capable of 3 A of continuous operating current
as long as T
J
is less than 70°C. At 85°C, the rated current drops
to 2.22 A.
The overtemperature protection circuit activates if the load cur-
rent causes the junction temperature to exceed 125°C. When
this occurs, the overtemperature protection circuitry disables
the output until the junction temperature falls below approximately
110°C, at which point the output is reenabled. If the fault condition
persists, the output cycles off and on until the fault is removed.
The ADP197-02 incorporates a QOD circuit to discharge the
output capacitance when the ADP197-02 output is disabled.
ESD protection structures are shown in the block diagram as Zener
diodes.
The ADP197 is a low quiescent current device with a nominal
4 MΩ pull-down resistor on its EN pin. The package is a space-
saving 1.0 mm × 1.5 mm, 0.5 mm pitch, 6-ball WLCSP and a
tiny 2.0 mm × 2.0 mm × 0.55 mm, 0.65 mm pitch, 6-lead LFCSP.
Data Sheet ADP197
Rev. C | Page 11 of 13
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP197 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used capa-
citors when the effective series resistance (ESR) value is carefully
considered. The ESR of the output capacitor affects the response
to load transients. A typical 1 µF capacitor with an ESR of 0.1 Ω
or less is recommended for good transient response. Using a larger
value of output capacitance improves the transient response to
large changes in load current.
Input Bypass Capacitor
Connecting at least 1 µF of capacitance from VIN to GND reduces
the circuit sensitivity to the printed circuit board (PCB) layout,
especially when high source impedance or long input traces are
encountered. When greater than 1 µF of output capacitance is
required, increase the input capacitor to match it.
GROUND CURRENT
The major source for ground current in the ADP197 is the internal
charge pump for the FET drive circuitry. Figure 26 shows the
typical ground current when V
EN
= V
IN
, and varies from 1.8 V
to 5.5 V.
0
5
10
15
20
25
30
35
40
45
50
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
GROUND CURRENT (µA)
V
IN
(V)
09298-024
50mA
100mA
200mA
500mA
1000mA
3000mA
Figure 26. Ground Current vs. Input Voltage (V
IN
), Different Load Currents
ENABLE FEATURE
The ADP197 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. As shown in Figure 27,
when a rising voltage (V
EN
) on the EN pin crosses the active
threshold, VOUT turns on. When a falling voltage (V
EN
) on
the EN pin crosses the inactive threshold, VOUT turns off.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0 0.2 0.4 0.6 0.8 1.0 1.2
V
OUT
(V)
ENABLE VOLTAGE (V)
V
EN
FALLING
V
EN
RISING
V
OUT
AT 3.6V
09298-025
Figure 27. Typical EN Operation
As shown in Figure 27, the EN pin has hysteresis built into it.
This built-in hysteresis prevents on/off oscillations that can
occur due to noise on the EN pin as it passes through the
threshold points.
The EN pin active and inactive thresholds derive from the V
IN
voltage; therefore, these thresholds vary with the changing input
voltage. Figure 28 shows the typical EN active and inactive
thresholds when the input voltage varies from 1.8 V to 5.5 V.
0
0.2
0.4
0.6
0.8
1.0
1.2
1.82.22.63.03.43.84.24.65.05.4
ENABLE TH
R
ESHOLD (V)
INPUT VOLTAGE (V)
EN RISE
EN FALL
09298-026
Figure 28. Typical EN Threshold vs. Input Voltage (V
IN
)

ADP197CP-EVALZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Management IC Development Tools ADP197 Evaluati on Board
Lifecycle:
New from this manufacturer.
Delivery:
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