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ADR395BUJZ-R2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ADR391/ADR392/ADR395
Rev. H | Page 13 of 20
TERMINOLOGY
Temperature Coefficient
The change of output voltage with respect to operating temperature
changes normalized by the output voltage at 25°C. This parameter
is expressed in ppm/°C and can be determined by
[]
() ()
()
()
6
10
–C25
–
Cppm/ ×
×°
=°
12
O
1
O
2
O
O
TTV
TVTV
TCV (1)
where:
V
O
(25°C) is V
O
at 25°C.
V
O
(T
1
) is V
O
at Temperature 1.
V
O
(T
2
) is V
O
at Temperature 2.
Line Regulation
The change in output voltage due to a specified change in input
voltage. This parameter accounts for the effects of self-heating.
Line regulation is expressed in either percent per volt, parts-per-
million per volt, or microvolts per volt change in input voltage.
Load Regulation
The change in output voltage due to a specified change in load
current. This parameter accounts for the effects of self-heating.
Load regulation is expressed in either microvolts per milliampere,
parts-per-million per milliampere, or ohms of dc output resistance.
Long-Term Stability
Typical shift of output voltage at 25°C on a sample of parts
subjected to a test of 1000 hours at 25°C.
Δ
V
O
= V
O
(t
0
) − V
O
(t
1
)
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×
−
=Δ
6
10
)(
)()(
]ppm[
0
O
1
O
0
O
O
tV
tVtV
V
(2)
where:
V
O
(t
0
) is V
O
at 25°C at Time 0.
V
O
(t
1
) is V
O
at 25°C after 1000 hours operation at 25°C.
Thermally Induced Output Voltage Hysteresis
The change of output voltage after the device cycles through
the temperatures from +25°C to –40°C to +125°C and back to
+25°C. This is a typical value from a sample of parts put through
such a cycle.
V
O_HYS
= V
O
(25°C) − V
O_TC
(3)
6
_
_
10
)25(
)25(
]ppm[ ×
−
=
CV
VCV
V
O
TCO
O
HYSO
o
o
(4)
where:
V
O
(25°C) is V
O
at 25°C.
V
O_TC
is V
O
at 25°C after a temperature cycle from +25°C to
−40°C to +125°C and back to +25°C.
ADR391/ADR392/ADR395
Rev. H | Page 14 of 20
THEORY OF OPERATION
Band gap references are the high performance solution for low
supply voltage and low power voltage reference applications,
and the ADR391/ADR392/ADR395 are no exception. The
uniqueness of these devices lies in the architecture. As shown in
Figure 33, the ideal zero TC band gap voltage is referenced to
the output, not to ground. Therefore, if noise exists on the
ground line, it is greatly attenuated on V
OUT
. The band gap cell
consists of the PNP pair, Q51 and Q52, running at unequal
current densities. The difference in V
BE
results in a voltage with
a positive TC, which is amplified by a ratio of
R54
R58
2 ×
This PTAT voltage, combined with V
BE
s of Q51 and Q52,
produces a stable band gap voltage.
Reduction in the band gap curvature is performed by the ratio
of Resistors R44 and R59, one of which is linearly temperature
dependent. Precision laser trimming and other patented circuit
techniques are used to further enhance the drift performance.
SHDN
R60
Q51
R54
R61
R53
Q52
R58
R59 R44
R48
R49
Q1
GND
00419-040
IN
V
OUT (FORCE)
V
OUT (SENSE)
Figure 33. Simplified Schematic
DEVICE POWER DISSIPATION CONSIDERATIONS
The ADR391/ADR392/ADR395 are capable of delivering load
currents to 5 mA, with an input voltage that ranges from 2.8 V
(ADR391 only) to 15 V. When these devices are used in
applications with large input voltages, care should be taken to
avoid exceeding the specified maximum power dissipation or
junction temperature because it could result in premature
device failure. The following formula should be used to
calculate the maximum junction temperature or dissipation of
the device:
JA
A
J
D
TT
P
θ
=
–
(5)
where:
T
J
and T
A
are, respectively, the junction and ambient temperatures.
P
D
is the device power dissipation.
θ
JA
is the device package thermal resistance.
SHUTDOWN MODE OPERATION
The ADR391/ADR392/ADR395 include a shutdown feature
that is TTL/CMOS level compatible. A logic low or a zero volt
condition on the
SHDN
pin is required to turn the devices off.
During shutdown, the output of the reference becomes a high
impedance state, where its potential would then be determined
by external circuitry. If the shutdown feature is not used, the
SHDN
pin should be connected to V
IN
(Pin 2).
ADR391/ADR392/ADR395
Rev. H | Page 15 of 20
APPLICATIONS INFORMATION
BASIC VOLTAGE REFERENCE CONNECTION
The circuit shown in Figure 34 illustrates the basic configuration
for the ADR39x family. Decoupling capacitors are not required
for circuit stability. The ADR39x family is capable of driving
capacitive loads from 0 μF to 10 μF. However, a 0.1 μF ceramic
output capacitor is recommended to absorb and deliver the
charge, as required by a dynamic load.
S
HUTDOWN
INPUT
C
B
0.1µF
C
B
0.1µF
*
*
OUTPUT
*NOT REQUIRED
ADR39x
SHDN
GND
V
OUT (SENSE)
V
IN
V
OUT (FORCE)
00419-041
Figure 34. Basic Configuration for the ADR39x Family
Stacking Reference ICs for Arbitrary Outputs
Some applications may require two reference voltage sources,
which are a combined sum of standard outputs. Figure 35 shows
how this stacked output reference can be implemented.
GND
U2
U1
C2
0.1µF
C2
0.1µF
OUTPUTTABLE
U1/U2
SHDN
V
OUT (SENSE)
V
OUT (FORCE)
V
IN
V
OUT1
V
OUT2
V
IN
V
OUT1
(V) V
OUT2
(V)
ADR391/ADR391
ADR392/ADR392
ADR395/ADR395
2.5
4.096
5
5.0
8.192
10
00419-042
GND
SHDN
V
OUT (SENSE)
V
OUT (FORCE)
V
IN
Figure 35. Stacking Voltage References with the ADR391/ADR392/ADR395
Two reference ICs are used, fed from an unregulated input, V
IN
.
The outputs of the individual ICs are connected in series, which
provide two output voltages, V
OUT1
and V
OUT2
. V
OUT1
is the
terminal voltage of U1, while V
OUT2
is the sum of this voltage
and the terminal voltage of U2. U1 and U2 are chosen for the
two voltages that supply the required outputs (see the Output
Table in Figure 35). For example, if both U1 and U2 are ADR391s,
V
OUT1
is 2.5 V and V
OUT2
is 5.0 V.
While this concept is simple, a precaution is required. Because
the lower reference circuit must sink a small bias current from
U2 plus the base current from the series PNP output transistor
in U2, either the external load of U1 or an external resistor must
provide a path for this current. If the U1 minimum load is not
well defined, the external resistor should be used and set to a
value that conservatively passes 600 μA of current with the
applicable V
OUT1
across it. Note that the two U1 and U2
reference circuits are treated locally as macrocells; each has its
own bypasses at input and output for best stability. Both U1 and
U2 in this circuit can source dc currents up to their full rating.
The minimum input voltage, V
IN
, is determined by the sum of
the outputs, V
OUT2
, plus the dropout voltage of U2.
A Negative Precision Reference without Precision Resistors
A negative reference can be easily generated by adding an A1
op amp and is configured as shown in Figure 36. V
OUT (FORCE)
and V
OUT (SENSE)
are at virtual ground and, therefore, the negative
reference can be taken directly from the output of the op amp.
The op amp must be dual-supply, low offset, and rail-to-rail if
the negative supply voltage is close to the reference output.
GND
A1
SHDN
+
V
DD
V
OUT (FORCE)
V
OUT (SENSE)
–V
DD
V
IN
–V
REF
00419-043
Figure 36. Negative Reference
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ADR395BUJZ-R2

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Voltage References 5V Micropower Prec Low Noise w/ Shutdwn
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