10
FN4766.3
December 27, 2004
Under-Voltage
The VSEN pin also detects when the CORE voltage falls
more than 10% below the VID programmed level. This
causes PGOOD to go low, but has no other effect on
operation and is not latched. There is also hysteresis in this
detection point.
Over-Current
In the event of an over-current condition, the over-current
protection circuit reduces the average current delivered to
less than 25% of the current limit. When an over-current
condition is detected, the controller forces all PWM outputs
into a three state mode. This condition results in the gate
driver removing drive to the output stages.The HIP6302
goes into a wait delay timing cycle that is equal to the Soft-
Start ramp time. PGOOD also goes “low” during this time
due to VSEN going below its threshold voltage.To lower the
average output dissipation, the Soft-Start initial wait time is
increased from 32 to 2048 cycles, then the Soft-Start ramp is
initiated. At a PWM frequency of 200kHz, for instance, an
over-current detection would cause a dead time of 10.24ms,
then a ramp of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
Soft-Start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, over-current is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal Soft-Start cycle.
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID2, VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
V
CC
by an internal 20µA current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is ±1% accurate over
the operating temperature and voltage range.
PGOOD
SHORT
50A/DIV
CURRENT
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
SUPPLY FREQUENCY = 200kHz, V
IN
= 12V
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SHORT APPLIED HERE
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4 VID3 VID2 VID1 VID0 VDAC
11111Off
111101.100
111011.125
111001.150
110111.175
110101.200
110011.225
110001.250
101111.275
101101.300
101011.325
101001.350
100111.375
100101.400
100011.425
100001.450
011111.475
011101.500
011011.525
011001.550
010111.575
010101.600
010011.625
010001.650
001111.675
001101.700
001011.725
001001.750
000111.775
000101.800
000011.825
000001.850
HIP6302HIP6302
11
FN4766.3
December 27, 2004
Current Sensing and Balancing
Overview
The HIP6302 samples the on-state voltage drop across each
synchronous rectifier FET, Q2, as an indication of the
inductor current in that phase, see Figure 7. Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x inductor current (I
L
). Note that I
L
, the
inductor current, is 1/2 of the total current (I
LT
).
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the HIP6302
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x r
DS(ON)
(Q2) / R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an over-current condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the I
L
currents in the two phases
Over-Current, Selecting R
ISEN
The current detected through the R
ISEN
resistor is averaged
with the current detected in the other channel. The averaged
current is compared with a trimmed, internally generated
current, and used to detect an over-current condition.
The nominal current through the R
ISEN
resistor should be
50µA at full output load current, and the nominal trip point for
over-current detection is 165% of that value, or 82.5µA.
Therefore, R
ISEN
= I
L
x
r
DS(ON)
(Q2)/50µA.
For a full load of 25A per phase, and an r
DS(ON)
(Q2) of
4m, R
ISEN
= 2k.
The over-current trip point would be 165% of 25A, or ~ 41A
per phase. The R
ISEN
value can be adjusted to change the
over-current trip point, but it is suggested to stay within ±25%
of nominal.
Droop, Selection of R
IN
The average of the currents detected through the R
ISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for R
IN
, so the average
current creates a voltage drop across R
IN
. This drop
increases the apparent V
CORE
voltage with increasing load
current, causing the system to decrease V
CORE
to maintain
balance at the FB pin. This is the desired “droop” voltage
used to maintain V
CORE
within limits under transient
conditions.
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
CURRENT
SENSING
COMPARATOR
PWM
CIRCUIT
AVERAGING
CURRENT
FROM
OTHER
CHANNEL
SAWTOOTH
GENERATOR
+
DIFFERENCE
R
ISEN
+
CORRECTION
ERROR
AMPLIFIER
FB
COMP
REFERENCE
TO OTHER
CHANNELS
I
SEN
R
IN
R
FB
C
c
V
CORE
Q1
Q2
COMPARATOR
REFERENCE
TO OVER
CURRENT
TRIP
L
01
PHASE
INDUCTOR
CURRENT
FROM
OTHER
CHANNEL
PWM
I
L
DAC
HIP6302
C
OUT
R
LOAD
V
IN
ONLY ONE OUTPUT
HIP6601
-
-
STAGE SHOWN
-
+
SENSING
-
+
-
+
HIP6302HIP6302
12
FN4766.3
December 27, 2004
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage
occur at the leading and trailing edges of the load transient. In
order to fully utilize the output-voltage tolerance range, the
output voltage is positioned in the upper half of the range
when the output is unloaded and in the lower half of the range
when the controller is under full load. This droop
compensation allows larger transient voltage deviations and
thus reduces the size and cost of the output filter components.
R
IN
should be selected to give the desired “droop” voltage at
the normal full load current 50µA applied through the R
ISEN
resistor (or at a different full load current if adjusted as under
“Over-Current, Selecting R
ISEN
” above).
R
IN
= Vdroop / 50µA
For a Vdroop of 80mV, R
IN
= 1.6k
The AC feedback components, R
FB
and Cc, are scaled in
relation to R
IN
.
Current Balancing
The detected currents are also used to balance the phase
currents.
Each phase’s current is compared to the average of the two
phase currents, and the difference is used to create an offset
in that phase’s PWM comparator. The offset is in a direction
to reduce the imbalance.
The balancing circuit can not make up for a difference in
r
DS(ON)
between synchronous rectifiers. If a FET has a
higher r
DS(ON)
, the current through that phase will be
reduced.
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to
the load current divided by the number of phases (I
LT
/ n),
and a sawtooth current, (i
PK-PK
) resulting from switching.
The sawtooth component is dependent on the size of the
inductors, the switching frequency of each phase, and the
values of the input and output voltage. Ignoring secondary
effects, such as series resistance, the peak to peak value of
the sawtooth current can be described by:
i
PK-PK
= (V
IN
x V
CORE
- V
CORE
2
) / (L x F
SW
x V
IN
)
Where: V
CORE
= DC value of the output or V
ID
voltage
V
IN
= DC value of the input or supply voltage
L = value of the inductor
F
SW
= switching frequency
Example: For V
CORE
= 1.6V,
V
IN
= 12V,
L= 1.3µH,
F
SW
= 250kHz,
Then i
PK-PK
= 4.3A
The inductor, or load current, flows alternately from V
IN
through Q1 and from ground through Q2. The HIP6302
samples the on-state voltage drop across each Q2 transistor
to indicate the inductor current in that phase. The voltage
drop is sampled 1/3 of a switching period, 1/F
SW
, after Q1 is
turned OFF and Q2 is turned on. Because of the sawtooth
current component, the sampled current is different from the
average current per phase. Neglecting secondary effects,
the sampled current (I
SAMPLE
) can be related to the load
current (I
LT
) by:
I
SAMPLE
=
I
LT
/ n +
(V
IN
V
CORE
- 3V
CORE
2
) / (6L x F
SW
x V
IN
)
Where: I
LT
= total load current
n = the number of channels
Example: Using the previously given conditions, and
For I
LT
= 50A,
n= 2
Then I
SAMPLE
= 25.49A
0
5
10
15
20
25
AMPERES
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING DISABLED
0
5
10
15
20
25
AMPERES
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING ENABLED
HIP6302HIP6302

HIP6302CBZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers VER OF HIP6302CB-T
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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