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STCF03ITBR

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Introduction STCF03I
19/33
7.12 Reading from multiple registers with incremental addressing
Reading from multiple registers starts in the same way like reading from a single register. As
soon as the first register is read, the register address is automatically increased. If the
master generates an acknowledge pulse after receiving the data from the first register, then
reading of the next register can start immediately without sending the device address and
the register address again. The last acknowledge pulse before the STOP bit is not required.
See the Figure 12.
Figure 11. Reading from a single register
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS
OF
REGISTER
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits
DATA
L
S
B
S
T
O
P
N
O
A
C
K
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS
OF
REGISTER
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits
DATA
L
S
B
S
T
O
P
N
O
A
C
K
SDA LINE
Figure 12. Reading from multiple registers
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS OF
REGISTER i
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits
DATA i
A
C
K
S
T
O
P
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
N
O
A
C
K
SDA LINE
S
T
A
R
T
DEVICE
ADDRESS
7 bits
A
C
K
W
R
I
T
E
M
S
B
L
S
B
R
/
W
ADDRESS OF
REGISTER i
A
C
K
M
S
B
L
S
B
S
T
A
R
T
A
C
K
R
/
W
R
E
A
D
DEVICE
ADDRESS
7 bits
DATA i
A
C
K
S
T
O
P
L
S
B
DATA i+1
A
C
K
L
S
B
DATA i+2
A
C
K
L
S
B
DATA i+2
L
S
B
DATA i+n
M
S
B
M
S
B
M
S
B
M
S
B
A
C
K
L
S
B
N
O
A
C
K
SDA LINE
Obsolete Product(s) - Obsolete Product(s)
Description of internal registers STCF03I
20/33
8 Description of internal registers
8.1 PWR_ON
When set, it activates all analog and power internal blocks including the NTC supporting
circuit, and the device is ready to operate (ready mode). As long as PWR_ON=0, only the
I²C interface is active, minimizing Stand-by Mode power consumption.
8.2 TRIG_EN
This bit is AND-ed with the TRIG pin to generate the internal signal FL_ON that activates
flash mode. By this way, both soft-triggering and hard-triggering of the flash are made
possible. If soft-triggering (through I²C) is chosen, the TRIG pin is not used and must be
kept HIGH (VI). If hard-triggering is chosen, then the TRIG pin has to be connected to a µP
I/O devoted to flash timing control, and the TRIG_EN bit must be set in advance. Both
triggering modes can benefit of the internal flash time counter, that uses the TRIG_EN bit
and can work either as a safety shut-down timer or as a flash duration timer. Flash mode
can start only if PWR_ON=1. LED current is controlled by the value set by the FDIM_0~3 of
the DIM_REG.
8.3 TCH_ON
When set from ready mode, the STCF03I enters torch mode. The LED current is controlled
by the value set by the TDIM_0~3 of the DIM_REG.
8.4 NTC_ON
When the NTC_ON bit is set to HIGH and the device is in ready mode, then the comparators
that monitor the LED temperature are activated. NTC-related blocks are always active
regardless of this bit in torch mode and flash mode.
Table 9. I²C register mapping function
Register name SUB ADDRESS (hex) Operation
CMD_REG 00 R / W
DIM_REG 01 R / W
AUX_REG 02 R / W
STAT_REG 03 R only
Table 10. Command register
CMD_REG
(write mode)
MSB LSB
SUB ADD=00 PWR_ON TRIG_EN TCH_ON NTC_ON FTIM_3 FTIM_2 FTIM_1 FTIM_0
Power ON
RESET Value
0 0 000000
Obsolete Product(s) - Obsolete Product(s)
Description of internal registers STCF03I
21/33
8.5 FTIM_0~3
This 4-bits register defines the maximum flash duration. It is intended to limit the energy
dissipated by the LED to a maximum safe value or to leave to the STCF03I the control of the
flash duration during normal operation. Values from 0~15 correspond to 0~1.5 s (100 ms
steps). The timing accuracy is related to the internal oscillator frequency that clocks the
flash time counter (+/-20%, TBD). Entering flash mode (either by soft or hard triggering)
activates the flash time counter, which begins counting down from the value loaded in the
F_TIM register. When the counter reaches zero, flash mode is stopped by resetting
TRIG_EN bit, and simultaneously the ATN pin is set to true (LOW) to alert the µP that the
maximum time has been reached. FTIM value remains unaltered at the end of the count.
8.6 TDIM_0~3
These 4 bits define the LED current in torch mode with 16 values fitting an exponential law.
Max torch current value is 25% of max flash current. (Figure 13)
8.7 FDIM_0~3
These 4 bits define the LED current in flash mode with 16 values fitting an exponential law.
The max value of the current is set by the external resistors R
FL
and R
TR
. (Figure 13)
Note: LED current values refer to R
FL
=0.27 Ω, R
TR
=1.8 Ω
Table 11. Dimming register
DIM_REG
(write mode)
MSB LSB
SUB ADD=01 TDIM_3 TDIM_2 TDIM_1 TDIM_0 FDIM_3 FDIM_2 FDIM_1 FDIM_0
Power ON,
SHUTDOWN MODE
RESET Value
00000000
Figure 13. Flash and Torch current vs. dimming value
Current Step Coefficient - 1.19
Obsolete Product(s) - Obsolete Product(s)
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STCF03ITBR

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Manufacturer:
STMicroelectronics
Description:
IC LED DRIVER RGLTR DIM 25TFBGA
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