age. Use separate analog and digital PC board ground
sections with only one star point (Figure 14) connecting
the two ground systems (analog and digital). For lowest
noise operation, ensure the ground return to the star
ground’s power supply is low impedance and as short
as possible. Route digital signals far away from sensi-
tive analog and reference inputs.
High-frequency noise in the power supply (V
DD
) could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
DD
to the star ground with a network of
two parallel capacitors, 0.1µF and 4.7µF, located as
close as possible to the MAX1236–MAX1239 power-sup-
ply pin. Minimize capacitor lead length for best supply
noise rejection, and add an attenuation resistor (5Ω) in
series with the power supply if it is extremely noisy.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This straight
line can be either a best straight-line fit or a line drawn
between the endpoints of the transfer function, once offset
and gain errors have been nullified. The MAX1236–
MAX1239’s INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t
AD
) is the time between the falling
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNR
MAX[dB]
= 6.02
dB
N + 1.76
dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals.
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
______________________________________________________________________________________ 19
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS
0
INPUT VOLTAGE (LSB)
OUTPUT CODE
ZS = 0
+FS - 1 LSB
V
COM
V
REF
/2
V
IN
= (AIN+) - (AIN-)
FS
=
V
REF
2
-FS =
-V
REF
2
MAX1236-MAX1239
1 LSB =
V
REF
4096
Figure 13. Bipolar Transfer Function
GND
V
LOGIC
= 3V/5V3V OR 5V
SUPPLIES
DGND3V/5VGND
*OPTIONAL
4.7μF
R* = 5Ω
0.1μF
V
DD
DIGITAL
CIRCUITRY
MAX1236–
MAX1239
Figure 14. Power-Supply Grounding Connection
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
20 ______________________________________________________________________________________
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
THD
VVVV
V
log
+++
20
2
2
3
2
4
2
5
2
1
SINAD dB
SignalRMS
NoiseRMS THDRMS
( ) log
+
20
*RC NETWORK IS OPTIONAL
**AIN11/REF (MAX1238/MAX1239)
*R
S
*R
S
ANALOG
INPUTS
μC
SDA
SCL
GND
RC NETWORK*
V
DD
SDA
SCL
2kΩ
AIN0
AIN1
AIN3**/REF
3.3V or 5V
5V
R
P
C
REF
R
P
5V
MAX1236
MAX1237
MAX1238
MAX1239
0.1μF
0.1μF
Typical Operating Circuit
SDA
SCLAIN3/REF
1
2
8
7
V
DD
GNDAIN1
AIN2
AIN0
MAX
TOP VIEW
3
4
6
5
MAX1236
MAX1237
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AIN0 AIN8
AIN9
AIN10
AIN11/REF
V
DD
GND
SDA
SCL
MAX1238
MAX1239
QSOP
AIN1
AIN2
AIN5
AIN3
AIN4
AIN6
AIN7
Pin Configurations
MAX1236–MAX1239
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
______________________________________________________________________________________ 21
Chip Information
PROCESS: BiCMOS
MAX1236–MAX1239
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages
. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 µMAX U8+1
21-0036
16 QSOP E16+4
21-0055

MAX1238EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 12Ch 94.4ksps 5.5V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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