X9440WS24I Datasheet X9440WS24I, X9440WS24I-2.7, X9440WV24 | P4-P6

FN8200.0

March 28, 2005

REGISTERS

Both digitally-controlled potentiometers and voltage com-

parators share the serial interface and share a common

architecture. Each potentiometer and voltage comparator

is associated with wiper counter and analog control reg-

isters and eight data registers. A detailed discussion of

the register organization and array operation follows.

Wiper Counter (WCR) and Analog Control

Registers (ACR)

The X9440 contains two wiper counter registers: one

for each XDCP potentiometer and two Analog Control

Registers, and one for each of the two voltage com-

parators. The wiper counter register is equivalent to a

serial-in, parallel-out counter with its outputs decoded

to select one of sixty-four switches along its resistor

array. The contents of the wiper counter register and

analog control register can be altered in four ways: it

may be written directly by the host via the Write WCR

instruction (serial load); it may be written indirectly by

transferring the contents of one of four associated

data registers (DR) via the XFR data register instruc-

tion (parallel load); it can be modified one step at a

time by the increment/ decrement instruction (WCR

only). Finally, it is loaded with the contents of its data

The wiper counter and analog control register are vol-

atile registers; that is, their contents are lost when the

X9440 is powered-down. Although the registers are

automatically loaded with the value in R0 upon power-

up, it should be noted this may be different from the

value present at power-down.

Programming the ACR is similar to the WCR. How-

ever, the 6 bits in the WCR positions the wiper in the

resistor array while 3 bits in the ACR control the com-

parator and its output.

Data Registers (DR)

Each potentiometer and each voltage comparator has

four non volatile data registers (DR). These can be

read or written directly by the host and data can be

transferred between any of the four data registers and

the WCR or ACR. It should be noted all operations

changing data in one of these registers is a non vola-

tile operation and will take a maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer or comparator, these reg-

isters can be used as regular memory locations that

could store system parameters or user preference data.

Figure 1. Detailed Potentiometer Block Diagram

Serial Data Path

From Interface

Circuitry

Serial

Bus

Input

Parallel

Bus

Input

Counter

Inc/Dec

Logic

UP/DN

CLK

Modified SCK

UP/DN

8 6

If WC = 00[H] V

= V

If WC = 3F[H] V

= V

Wiper

(One of Two Arrays)

(WCR)

X9440

FN8200.0

March 28, 2005

Wiper Counter Register (WCR)

WP0-WP5 identify wiper position.

Analog Control Register (ACR)

Shutdown

“1” indicates power is connected to the voltage

comparator.

“0” indicates power is not connected to the voltage

comparator.

Enable

“1” indicates the output buffer of the voltage

comparator is enabled.

“0” indicates the output buffer of the voltage

comparator is disabled.

Latch

“1” indicates the output of the voltage comparator is

memorized or latched.

“0” indicates the output of the voltage comparator is

not latched.

Userbits—available for user applications

Data Registers (DR, R

-R

)

{Refer to Memory Map, Figure 9}

INSTRUCTIONS AND PROGRAMMING

Identification (ID) Byte

The first byte sent to the X9440 from the host, follow-

ing a CS

going HIGH to LOW, is called the Identifica-

tion byte. The most significant four bits of the slave

address are a device type identifier, for the X9440 this

is fixed as 0101[B] (refer to Figure 2).

The two least significant bits in the ID byte select one

of four devices on the bus. The physical device

address is defined by the state of the A

-A

input pins.

The X9440 compares the serial data stream with the

address input state; a successful compare of both

address bits is required for the X9440 to successfully

continue the command sequence. The A

-A

inputs

can be actively driven by CMOS input signals or tied to

or V

The remaining two bits in the slave byte must be set to 0.

Figure 2. Identification Byte Format

Instruction Byte

The byte following the address contains the instruction

and register pointer information. The four most signifi-

cant bits are the instruction. The next four bits point to

one of the two pots or two voltage comparators and

when applicable they point to one of four associated

registers. The format is shown below in Figure 3.

Figure 3. Instruction Byte Format

The four high order bits of the instruction byte specify

the operation. The next two bits (R

and R

) select one

of the four data registers that is to be acted upon when

a register oriented instruction is issued. The last two

bits (P

and P

) selects which one of the four potenti-

ometers is to be affected by the instruction.

The four high order bits define the instruction. The next

two bits (R

and R

) select one of the four data registers

that is to be acted upon when a register oriented instruc-

tion is issued. The last two bits (P

and P

) select which

one of the two potentiometers or which one of the two

voltage comparators is to be affected by the instruction.

0 0 WP5 WP4 WP3 WP2 WP1 WP0

(volatile) (LSB)

User-

bit5

User-

bit4

User-

bit3 Latch Enable

Shut-

down

(volatile) (LSB)

Wiper Position or Analog Control Data or User Data

(Nonvolatile)

100

0 0 A1 A0

Device Type

Identifier

Device Address

I1I2I3 I0 R1 R0 P1 P0

Pot Select

Select

Instructions

X9440

FN8200.0

March 28, 2005

Four of the ten instructions end with the transmission

of the instruction byte. The basic sequence is illus-

trated in Figure 4. These two-byte instructions

exchange data between the wiper counter register or

analog control register and one of the data registers. A

transfer from a data register to a wiper counter register

or analog control register is essentially a write to a

static RAM. The response of the wiper to this action

will be delayed t

WRL

. A transfer from the wiper counter

write to non volatile memory and takes a minimum of

to complete. The transfer can occur between one

of the two potentiometers or one of the two voltage

comparators and one of its associated registers; or it

may occur globally, wherein the transfer occurs

between both of the potentiometers and voltage com-

parators and one of their associated registers.

Five instructions require a three-byte sequence to

complete. These instructions transfer data between

the host and the X9440; either between the host and

one of the data registers or directly between the host

and the wiper counter and analog control registers.

These instructions are: Read Wiper Counter Register

or Analog Control Register, read the current wiper

position of the selected pot or the comparator control

bits, Write Wiper Counter Register or Analog Control

selected pot or control the voltage comparator; Read

Data Register, read the contents of the selected non

volatile register; Write Data Register, write a new value

to the selected data register. The bit structures of the

instructions are shown in Figure 9.

The sequences of the three byte operations are shown

in Figure 5 and Figure 6.

The bit structures of the instructions and the descrip-

tion of the instructions are shown in Figure 10.

Figure 4. Two-Byte Command Sequence

Figure 5. Three-Byte Command Sequence (Write)

010100A1A0 I3 I2 I1 I0 R1 R0 P1 P0

SCK

0101

A1 A0

I3 I2 I1 I0 R1 R0 P1 P0

SCL

0 0 D5 D4 D3 D2 D1 D0

X9440

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

X9440WS24I

Mfr. #:

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Manufacturer:

Renesas / Intersil

Description:

IC DUAL PROG COMP 10K 64TP SO24

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