73S8009CN-DB Datasheet 73S8009CN-DB | P13-P15

UM_8009CN_060 73S8009CN Demo Board User Manual

Rev. 1.1 13

4.4 ON/OFF Switch Operation

The ON/OFF switch uses a pushbutton to toggle between turning the 73S8009CN on and off. The switch

input contains a debounce circuit for protection. The 73S8009CN defaults to the OFF state when the

power source is applied. When the 8009C is in the OFF state, a switch closure turns on the 73S8009CN.

When the 73S8009CN is ON, a switch closure does not turn off the 73S8009CN by itself, but it activates

the OFF_REQ signal by setting it high. The 73S8009CN does not shut off until the OFF_ACK is set high.

The purpose of this sequence is to allow the host processor to perform any necessary shut down tasks

before losing power. When the host is finished, it can set the OFF_ACK signal high to shut off the

73S8009CN. If there is no need for the host to perform any shutdown tasks, the OFF_ACK pin can be

left open and it follows the state of the OFF_REQ output by means of an internal resistor connection

between the OFF_REQ and OFF_ACK pins.

73S8009CN Demo Board User Manual UM_8009CN_060

14 Rev. 1.1

1

2

S1 SW

1

2

JP7

CS

Disable

Note: VPCIN

must be

between 2.7

and 6.5V

3.3V

1

2

JP1

SIM Force

Detect

1

2

3

4

5

6

7

8

9

10

J4

TSM_110_01_L_SV

C12

27pF

C3

0.1uF

R6 47K

VPCIN

+

C1 10uF

3.3V

VPC

SELECT

L1

3.3V

CMDVCC%

1

2

TP2

1

2

3

4

5

6

7

8

9

10

J3

SSM_110_L_SV

AUX1UC

AUX2UC

IOUC

RDY

OFF_ACK

R13

Rd

R10

Ru

1

TP9

AUX1

AUX2

IO

CLKIN

C9

27pF

CMDVCC#

OFF

R14

100K

1

2

TP1

C11

0.47uF

RST

1

TP10

CLK

R5 47K

CSCS

C5

0.1uF

R4 1K

C2 0.1uF

RSTIN

1

2

TP3

VCC

1

RST

2

CLK

3

C4

4

GND

5

VPP

6

I/O

7

C8

8

SW-1

9

SW-2

10

J5

Smart Card Connector

VCC

Note: Pin 5 to 8 are near edge of board.

R8

Ru

R9

Ru

R11

Rd

VPCIN

R12

Rd

C1

1

C2

2

C3

3

C4

4

C5

5

C6

6

C7

7

C8

8

J6

SIM/SAM Connector

R1 10K

R7 0

SCIOEN

R3 47K

IOUC

1

AUX1UC

2

AUX2UC

3

CMDVCC5B

4

CMDVCC3B

5

RSTIN

6

CLKIN

7

RDY

8

OFF_ACK

9

TEST1

10

OFF_REQ

11

CS

12

SCIOENABLE

13

PRES

14

VP

15

GND

17

RST

18

VCC

19

DM

23

AUX2

20

DP

25

AUX1

21

I/O

22

ON/OFF

24

VPC

26

LIN

27

GND

28

VDD

29

TEST2

30

GND

31

OFFB

32

CLK

16

SLUG

33

U1

73S8009CN

R2 47K

1

2

3

4

5

6

7

8

9

10

J1

SSM_110_L_SV

CMDVCC5

OFF_REQ

C4

4.7uF

1

2

TP5

1

2

3

JP3

1

2

TP7

1

2

TP8

1

2

TP4

1

2

TP6

1

2

JP4

3.3VNote: JP4 pins 1

and 2 must not be

connected with JP2

pins 1 and 2 at the

same time.

GND

D-

2

D+

3

GND

4

VCC

1

GND

5

GND

6

J7

USB_CONN_4

D-

GND

C8

DNI

D+

+5VDC

SC4

TP3 to TP8, C9, C11 and

C12 are to be placed

very close to the pads

of J5

CLK

RDY

VDD

1

2

3

JP2

OFF_ACK

GND

R8 to R13 and C36 to be

placed within 1cm of

J7.

DNI

J1 must be aligned with J2 and J3 must be

aligned with J4 in order for this daughter

board to be stacked on another.

OFF_REQ

+3.3V

DNI

CS

DNI

RSTIN

VPCIN

J1 and J3 are placed on the bottom. J2 and J4

are placed on the top side.

RST

VPCIN

GND

J1 and J3 must be aligned with J8 and J9 on the

1121 evaluation board (E1121T8) respectivly in

order for this board to be stacked on it.

CMDVCC3

DNI

VCC

SCLK

C4

C1, C2, C3 and L1 must be placed

within 5mm of the U1 pins and

connected by thick track (wider

than 0.5mm)

VDD

SC8

DNI

SIO

Note: JP4 pins 1

and 2 should only

be connected when

3.3V is not sourced

from the mating

board (if

applicable)

OFF

GND

1

2

3

4

5

6

7

8

9

10

J2

TSM_110_01_L_SV

I/O

5 73S8009CN Demo Board Schematics, PCB Layouts and Bill of

Materials

5.1 Schematics

Figure 4: 73S8009CN Electrical Schematic

UM_8009CN_060 73S8009CN Demo Board User Manual

Rev. 1.1 15

5.2 73S8009CN PCB Layouts

Figure 5: 73S8009CN Demo Board: Top View

Figure 6: 73S8009CN Demo Board: Bottom View

73S8009CN-DB

73S8009CN-DB

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