74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 4 of 26
NXP Semiconductors
74HC594; 74HCT594
8-bit shift register with output register
6. Pinning information
6.1 Pinning
Fig 5. Timing diagram
mbc323
Q7S
Q0
STR
SHR
STCP
DS
SHCP
Q1
Q6
Q7
Fig 6. Pin configuration SO16
Q1 V
CC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf611
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC594
74HCT594
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 5 of 26
NXP Semiconductors
74HC594; 74HCT594
8-bit shift register with output register
6.2 Pin description
Fig 7. Pin configuration SSOP16 Fig 8. Pin configuration DIP16
74HC594
74HCT594
Q1 V
CC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf613
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC594
74HCT594
Q1 V
CC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf614
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output 1
Q2 2 parallel data output 2
Q3 3 parallel data output 3
Q4 4 parallel data output 4
Q5 5 parallel data output 5
Q6 6 parallel data output 6
Q7 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output
SHR 10 shift register reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
STR 13 storage register reset (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
V
CC
16 supply voltage
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 6 of 26
NXP Semiconductors
74HC594; 74HCT594
8-bit shift register with output register
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH transition;
X = don’t care.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 °C the value of P
tot
derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of P
tot
derates linearly with 8 mW/K.
For SSOP16 packages: above 60 °C the value of P
tot
derates linearly with 5.5 mW/K.
Table 3. Function table
[1]
Function Input
SHR STR SHCP STCP DS
Clear shift register L X X X X
Clear storage register X L X X X
Load DS into shift register stage 0, advance previous stage data to the next stage H X X H or L
Transfer shift register data to storage register and outputs Qn X H X X
Shift register one count pulse ahead of storage register H H ↑↑X
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+ 0.5 V
[1]
- ±20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
> V
CC
+ 0.5 V
[1]
- ±20 mA
I
O
output current V
O
= 0.5 V to V
CC
+ 0.5 V
Serial data output Q7S - ±25 mA
Parallel data output - ±35 mA
I
CC
supply current Serial data output Q7S - 50 mA
Parallel data output - 70 mA
I
GND
ground current Serial data output Q7S - 50 mA
Parallel data output - 70 mA
T
stg
storage temperature 65 +150 °C
P
tot
total power dissipation T
amb
= 40 °C to +125 °C
[2]
- 500 mW

74HC594N,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC SHIFT REGISTER 8BIT 16DIP
Lifecycle:
New from this manufacturer.
Delivery:
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