HIP2122, HIP2123
7
FN7670.0
December 23, 2011
Timing Diagram
Switching Specifications V
DD
= V
HB
= 12V, V
SS
= V
HS
= 0V, RDT = 0k, No Load on LO or HO, Unless Otherwise Specified.
PARAMETERS
(see “Timing Diagram”) SYMBOL
TEST
CONDITIONS
T
J
= +25°C T
J
= -40°C to +125°C
UNITSMIN TYPE MAX
MIN
(Note 9)
MAX
(Note 9)
HO Turn-Off Propagation Delay
HI Falling to HO Falling
t
PLHO
-3250 - 60 ns
LO Turn-Off Propagation Delay
LO Falling to LO Falling
t
PLLO
-3250 - 60 ns
Minimum Dead-Time Delay (see Note 10)
HO Falling to LO Rising
t
DTHLmin
R
DT
= 80k,
HI 1 to 0, LI 0 to 1
15 35 50 10 60 ns
Minimum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
t
DTLHmin
R
DT
= 80k
Li 1 to 0, HI 0 to 1
15 25 50 10 60 ns
Maximum Dead-Rising Delay (see Note 10)
HO Falling to LO rising
t
DTHLmax
R
DT
= 8k,
HI 1 to 0, LI 0 to 1
150 220 300 - - ns
Maximum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
t
DTLHmax
R
DT
= 8k,
Li 1 to 0, HI 0 to 1
150 220 300 - - ns
Either Output Rise/Fall Time
(10% to 90%/90% to 10%)
t
RC,
t
FC
C
L
= 1nF - 10 - - - ns
Either Output Rise/Fall Time
(3V to 9V/9V to 3V)
t
R,
t
F
C
L
= 0.1mF - 0.5 0.6 - 0.8 µs
Bootstrap Diode Turn-On or Turn-Off Time t
BS
-10- - - ns
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising when the LI and HI inputs
transition simultaneously.
HI
HO
LO
EN
t
PH
t
R
90%
10%
t
F
90%
LI
10%
t
PL
t
DT
t
DT
t
R
AND t
F
FOR LO ARE NOT
SHOWN FOR CLARITY
