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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1995-2007, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Wide dynamic range (50 dB) DTMF Receiver
Call progress (CP) detection via cadence
indication
4-bit synchronous serial data output
Software controlled guard time for MT3x70B
Internal guard time circuitry for MT3x71B
Powerdown option (MT317xB & MT337xB)
4.194304 MHz crystal or ceramic resonator
(MT337xB and MT327xB)
External clock input (MT317xB)
Guarantees non-detection of spurious tones
Applications
Integrated telephone answering machine
End-to-end signalling
•Fax Machines
February 2007
Ordering Information
MT3170/71BE 8 Pin PDIP Tubes
MT3270/71BE 8 Pin PDIP Tubes
MT3370/71BS 18 Pin SOIC Tubes
MT3370/71BN 20 Pin SSOP Tubes
MT3370/71BSR 18 Pin SOIC Tape & Reel
MT3371BNR 20 Pin SSOP Tape & Reel
MT3270/71BE1 8 Pin PDIP* Tubes
MT3171BE1 8 Pin PDIP* Tubes
MT3170BE1 8 Pin PDIP** Tubes
MT3370/BN1 20 Pin SSOP* Tubes
MT3370/71BS1 18 Pin SOIC* Tubes
MT3370/71BSR1 18 Pin SOIC* Tape & Reel
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40°C to 85°C
MT3170B/71B, MT3270B/71B, MT3370B/71B
Wide Dynamic Range DTMF Receiver
Data Sheet
Figure 1 - Functional Block Diagram
PWDN
VDD
VSS
INPUT
OSC2
OSC1
(CLK)
MT3170B/71B and MT337xB only.
MT3270B/71B and MT337xB only.
Voltage
Bias Circuit
AGC
Anti-
alias
Filter
High
Group
Filter
Low
Group
Filter
Steering
Circuit
Digital
Detector
Algorithm
Code
Converter
and
Latch
Digital
Guard
Time
Parallel to
Serial
Converter
& Latch
Mux
Energy
Detection
Oscillator
and
Clock
Circuit
To All Chip Clocks
Dial
Tone
Filter
ESt
DStD
ACK
SD
or
MT3x71B only.
MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet
2
Zarlink Semiconductor Inc.
Description
The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary
code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The
MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires
external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a
delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be
clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector
output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope)
of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific
call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without
additional components. A power-down option is provided for the MT317xB and MT337xB.
Figure 2 - Pin Connections
Pin Description
Pin #
Name Description
337xBN 337xBS 327xB 317xB
3211INPUTDTMF/CP Input. Input signal must be AC coupled via
capacitor.
642-OSC2Oscillator Output.
7633OSC1
(CLK)
Oscillator/Clock Input. This pin can either be driven by:
1) an external digital clock with defined input logic levels.
OSC2 should be left open.
2) connecting a crystal or ceramic resonator between
OSC1 and OSC2 pins.
8944V
SS
Ground. (0V)
13 11 5 5 SD Serial Data/Call Progress Output. This pin serves the dual
function of being the serial data output when clock pulses are
applied after validation of DTMF signal, and also indicates
the cadence of call progress input. As DTMF signal lies in
the same frequency band as call progress signal, this pin
may toggle for DTMF input. The SD pin is at logic low in
powerdown state.
10
18
17
16
15
14
13
12
11
VDD
NC
NC
ESt/DStD
NC
ACK
NC
SD
NC
1
2
3
4
5
6
7
8
9
NC
INPUT
PWDN
OSC2
NC
OSC1
NC
NC
VSS
INPUT
PWDN
CLK
VSS
VDD
ACK
SD
INPUT
OSC2
OSC1
VSS
VDD
ESt/
ACK
SD
MT3170B/71B MT3270B/71B MT3370BS/71BS
8 PIN PLASTIC DIP
18 PIN PLASTIC SOIC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
NC
NC
INPUT
PWDN
NC
NC
OSC1
OSC2
VSS
20 PIN SSOP
NC
VDD
NC
NC
ACK
SD
NC
NC
ESt/DStD
DStD
ESt/
DStD
MT3370BN/71BN
NC
NC
MT3170B/71B, MT3270B/71B, MT3370B/71B Data Sheet
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Zarlink Semiconductor Inc.
Change Summary
The following table summarizes the changes from the August 2006 issue.
14 13 6 6 ACK Acknowledge Pulse Input. After ESt or DStD is high,
applying a sequence of four pulses on this pin will then shift
out four bits on the SD pin, representing the decoded DTMF
digit. The rising edge of the first clock is used to latch the 4-
bit data prior to shifting. This pin is pulled down internally.
The idle state of the ACK signal should be low.
16 15 7 7 ESt
(MT3x70B)
DStD
(MT3x71B)
Early Steering Output. A logic high on ESt indicates that a
DTMF signal is present. ESt is at logic low in powerdown
state.
Delayed Steering Output. A logic high on DStD indicates
that a valid DTMF digit has been detected. DStD is at logic
low in powerdown state.
18 18 8 8 V
DD
Positive Power Supply (5 V Typ.) Performance of the
device can be optimized by minimizing noise on the supply
rails. Decoupling capacitors across V
DD
and V
SS
are
therefore recommended.
1,2,5,9,
10,11,12,
15,17,19,20
1,5,7,8,
10, 12,
14,16,
17
--NCNo Connection. Pin is unconnected internally.
43-2PWDNPower Down Input. A logic high on this pin will power down
the device to reduce power consumption. This pin is pulled
down internally and can be left open if not used. ACK pin
should be at logic ’0’ to power down device.
Summary of MT3x70/71B Product Family
Device
Type
8 Pin 18 Pin 20 Pin PWDN
2 Pin
OSC
Ext
CLK
ESt DStD
MT3170B √√
MT3171B √√
MT3270B √√√
MT3271B √√
MT3370B √√√√√√
MT3371B √√√√√
Page Item Description
2 Figure 2 Added ordering codes to Pin Connection diagram.
2 “Pin Description“ Added 20 pin description to the table.
Pin Description
Pin #
Name Description
337xBN 337xBS 327xB 317xB

MT3371BNR1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Communication ICs - Various Pb Free WIDE DYN RANGE DTMFRCVR4.19Mhz
Lifecycle:
New from this manufacturer.
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