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AD7783BRU-REEL

P1-P3P4-P6P7-P9P10-P12P13-P13
–6–
AD7783
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
XTAL1
AD7783
REFIN(+)
REFIN(–)
AIN(+)
AIN(–)
IOUT1
IOUT2
IPIN
XTAL2
V
DD
GND
MODE
DOUT/RDY
CS
SCLK
RANGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1 XTAL1 Input to the 32.768 kHz Crystal Oscillator Inverter.
2 REFIN(+) Positive Reference Input. REFIN(+) can lie anywhere between V
DD
and GND + 1 V. The nominal refer-
ence voltage (REFIN(+) – REFIN(–)) is 2.5 V, but the part functions with a reference from 1 V to V
DD
.
3REFIN(–)Negative Reference Input. This reference input can lie anywhere between GND and V
DD
– 1 V.
4 AIN(+) Analog Input. AIN(+) is the positive terminal of the fully differential analog input pair AIN(+)/AIN(–).
5 AIN(–)Analog Input. AIN(–) is the negative terminal of the fully differential analog input pair AIN(+)/AIN(–).
6 IOUT1 Output from Internal 200 mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be
switched to this output using hardware control pin IPIN.
7 IOUT2 Output from Internal 200 mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be
switched to this output using hardware control pin IPIN.
8 IPIN Logic Input that Selects the Routing of the On-Chip Current Sources. When IPIN is tied to GND, IEXC1
is routed to IOUT1 and IEXC2 is routed to IOUT2. When IPIN is tied to V
DD
, IEXC1 is routed to
IOUT2 and IEXC2 is routed to IOUT1.
9 RANGE Logic Input that Configures the Input Range on the Internal PGA. With RANGE = 0, the full-scale input
range is ± 160 mV; the full-scale input range equals ± 2.56 V when RANGE = 1 for a 2.5 V reference.
10 SCLK Serial Clock Input/Output for Data Transfers from the ADC. When the device is operated in master mode,
SCLK is an output with one SCLK period equal to one XTAL period. In slave mode, SCLK is generated
by an external source. In slave mode, all the data can be transmitted on a continuous train of pulses. Alter-
natively, it can be a noncontinuous clock with the information being transmitted from the AD7783 in
smaller batches of data. SCLK is Schmitt triggered (slave mode), making the interface suitable for opto-
isolated applications.
11 CS Chip Select Input. CS is an active low logic input used to select the AD7783. When CS is low, the PLL
establishes lock and allows the AD7783 to initiate a conversion. When CS is high, the conversion is aborted,
DOUT and SCLK are three-stated, the AD7783 enters standby mode, and any conversion result in the
output shift register is lost.
12 DOUT/RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose in this interface. When a conver-
sion is initiated, DOUT/RDY goes high and remains high until the conversion is complete. DOUT/RDY will
then return low to indicate that valid data is available to be read from the device. In slave mode, this acts as
an interrupt to the processor, indicating that valid data is available. If data is not read after a conversion,
DOUT/RDY will go high before the next update occurs. In master mode, DOUT/RDY goes low for at
least half an SCLK cycle before the device produces SCLKs. When SCLK becomes active, data is output
on the DOUT/RDY pin. Data is output on the falling SCLK edge and is valid on the rising edge.
13 MODE The MODE pin selects master or slave mode of operation. When MODE = 0, the AD7783 operates in
master mode; the AD7783 is configured for slave mode when MODE = 1.
14 GND Ground Reference Point for the AD7783.
15 V
DD
Supply Voltage, 3 V or 5 V Nominal.
16 XTAL2 Output from the 32.768 kHz Crystal Oscillator Inverter.
REV. C
Typical Performance Characteristics–AD7783
–7–
8
7
0
8388039
8388721
8388687
8388657
8388615
8388579
8388547
8388499
8388449
8388382
8388754
8389110
8389033
8388985
8388941
8388906
8388874
8388841
8388805
8388779
6
5
4
3
2
1
9
TPC 1. Noise Distribution Histogram
ADC CIRCUIT INFORMATION
Overview
The AD7783 incorporates a S-D ADC channel, on-chip pro-
grammable gain amplifier, and on-chip digital filtering intended
for the measurement of wide dynamic range, low frequency
signals such as those in weigh-scale, strain gage, pressure trans-
ducer, or temperature measurement applications.
This ADC input is buffered and can be programmed to have an
input voltage range of ± 160 mV or ±2.56 V. The input channel
is configured as a fully differential input. Buffering the input
channel means that the part can accommodate significant source
impedances on the analog input and that R, C filtering (for
noise rejection or RFI reduction) can be placed on the analog
input if required. The device requires an external reference of
2.5 V nominal. Figure 3 shows the basic connections required
to operate the part.
AD7783
REFIN(+)
REFIN(–)
AIN(–)
AIN(+)
IOUT2
IOUT1
XTAL1
XTAL2
V
DD
DOUT/RDY
CS
SCLK
GND
POWER
SUPPLY
10␮F
0.1␮F
␮CONTROLLER
32.768kHz
CRYSTAL
6k⍀
10k⍀
IN–
OUT+
OUT–
IN+
Figure 3. Basic Connection Diagram
The output rate of the AD7783 (f
ADC
)
equals
f
ADC
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32 768 10 69 8 3
3
./
while the settling time equals
t
f
t
SETTLE
ADC
ADC
=
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¯
˜
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2
2
Normal-mode rejection is the major function of the digital filter
on the AD7783. Simultaneous 50 Hz and 60 Hz rejection of
better than 60 dB is achieved as notches are placed at both 50 Hz
and 60 Hz. Figure 4 shows the filter rejection.
Figure 4. Filter Profile (Filter Notches at Both
50 Hz and 60 Hz)
2.5
0
1.0 3.02.52.01.5 3.5 5.04.54.0
2.0
1.5
1.0
0.5
3.0
V
REF
(V)
RMS NOISE (␮V)
ⴞ160mV RANGE
ⴞ2.56V RANGE
V
DD
= 5V
V
REF
= 2.5V
T
A
= 25ⴗC
TPC 2. RMS Noise vs. Reference Input
REV. C
–8–
AD7783
NOISE PERFORMANCE
Table I shows the output rms noise and output peak-to-peak
resolution in bits (rounded to the nearest 0.5 LSB) for the two
input voltage ranges. The numbers are typical and are generated
at a differential input voltage of 0 V. The peak-to-peak reso-
lution figures represent the resolution for which there will be
no code flicker within a six-sigma limit. The output noise comes
from two sources. The first is the electrical noise in the semi-
conductor devices (device noise) used in the implementation of
the modulator. Secondly, when the analog input is converted
into the digital domain, quantization noise is added. The device
noise is at a low level and is independent of frequency. The
quantization noise starts at an even lower level but rises rapidly
with increasing frequency to become the dominant noise source.
Table I. Typical Output RMS Noise and
Peak-to-Peak Resolution vs. Input Range
Input Range
± 160 mV ± 2.56 V
Noise (mV) 0.65 2.30
Peak-to-Peak Resolution (Bits) 16.5 18.5
DIGITAL INTERFACE
The AD7783’s serial interface consists of four signals: CS,
SCLK, DOUT/RDY, and MODE. The MODE pin is used to
select the master/slave mode of operation. When the part is
configured as a master, SCLK is an output; SCLK is an input
when slave mode is selected. Data transfers take place with
respect to this SCLK signal. The DOUT/RDY line is used
for accessing data from the data register. This pin also functions
as a RDY line. When a conversion is complete, DOUT/RDY
goes low to indicate that data is ready to be read from the
AD7783’s data register. It is reset high when a read operation
from the data register is complete. It also goes high prior to
the updating of the output register to indicate when not to
read from the device to ensure that a data read is not attempted
while the register is being updated. The digital conversion is
also output on this pin.
CS is used to select the device and to place the device in standby
mode. When CS is taken low, the AD7783 is powered up, the
PLL locks, and the device initiates a conversion. The device will
continue to convert until CS is taken high. When CS is taken
high, the AD7783 is placed in standby mode, minimizing the
current consumption. The conversion is aborted, DOUT and
SCLK are three-stated, and the result in the data register is lost.
Figure 2 shows the timing diagram for interfacing to the AD7783
with CS used to decode the part.
MASTER MODE (MODE = 0)
In this mode, SCLK is provided by the AD7783. With CS low,
SCLK becomes active when a conversion is complete and gener-
ates 24 falling and rising edges. The DOUT/RDY pin, which is
normally high, goes low to indicate that a conversion is complete.
Data is output on the DOUT/RDY pin following the SCLK
falling edge and is valid on the SCLK rising edge. When the
24-bit word has been output, SCLK idles high until the next
conversion is complete. DOUT/RDY returns high and will remain
high until another conversion is available. It then operates as a
RDY signal again. The part will continue to convert until CS is
taken high. SCLK and DOUT/RDY are three-stated when CS is
taken high.
SLAVE MODE (MODE = 1)
In slave mode, the SCLK is generated externally. SCLK must
idle high between data transfers. With CS low, DOUT/RDY
goes low when a conversion is complete. Twenty-four SCLK
pulses are needed to transfer the digital word from the AD7783.
Twenty-four consecutive pulses can be generated or, alterna-
tively, the data transfer can be split into batches. This is useful
when interfacing to a microcontroller that uses 8-bit transfers.
Data is output following the SCLK falling edge and is valid on
the SCLK rising edge.
CIRCUIT DESCRIPTION
Analog Input Channel
The ADC has one fully differential input channel. It feeds into a
high impedance input stage of the buffer amplifier. As a result,
the ADC input can handle significant source impedances and is
tailored for direct connection to external resistive-type sensors,
such as strain gages or resistance temperature detectors (RTDs).
The absolute input voltage range on the ADC input is restricted
to a range between GND + 100 mV and V
DD
– 100 mV. Care
must be taken in setting up the common-mode voltage and input
voltage range so that these limits are not exceeded; otherwise,
there will be a degradation in linearity and noise performance.
Programmable Gain Amplifier
The output from the buffer on the ADC is applied to the input of
the on-chip programmable gain amplifier (PGA). The PGA gain
range is programmed via the RANGE pin. With an external 2.5 V
reference applied, the PGA can be programmed to have a bipolar
range of ± 160 mV (RANGE = 0) or ± 2.56 V (RANGE = 1).
These are the ranges that should appear at the input to the
on-chip PGA.
Bipolar Configuration/Output Coding
The analog input on the AD7783 accepts bipolar input voltage
ranges. Signals on the AIN(+) input of the ADC are referenced
REV. C
P1-P3P4-P6P7-P9P10-P12P13-P13

AD7783BRU-REEL

Mfr. #:
Buy AD7783BRU-REEL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Pin-Config 24-bit w/ Excitation Crnt Src
Lifecycle:
New from this manufacturer.
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