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AD7783BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P13
AD7783
–3–
Parameter AD7783B Unit Test Conditions
LOGIC INPUTS
All Inputs Except SCLK and XTAL1
2
V
INL
, Input Low Voltage 0.8 V max V
DD
= 5 V
0.4 V max V
DD
= 3 V
V
INH
, Input High Voltage 2.0 V min V
DD
= 3 V or 5 V
SCLK Only (Schmitt-Triggered Input)
2
V
T(+)
1.4/2 V min/V max V
DD
= 5 V
V
T(–)
0.8/1.4 V min/V max V
DD
= 5 V
V
T(+)
– V
T(–)
0.3/0.85 V min/V max V
DD
= 5 V
V
T(+)
0.95/2 V min/V max V
DD
= 3 V
V
T(–)
0.4/1.1 V min/V max V
DD
= 3 V
V
T(+)
– V
T(–)
0.3/0.85 V min/V max V
DD
= 3 V
XTAL1 Only
2
V
INL
, Input Low Voltage 0.8 V max V
DD
= 5 V
V
INH
, Input High Voltage 3.5 V min V
DD
= 5 V
V
INL
, Input Low Voltage 0.4 V max V
DD
= 3 V
V
INH
, Input High Voltage 2.5 V min V
DD
= 3 V
Input Currents ± 1 mA max V
IN
= V
DD
–70 mA max V
IN
= GND, Typically –40 mA at 5 V and
–20 mA at 3 V
Input Capacitance 10 pF typ All Digital Inputs
LOGIC OUTPUTS (Excluding XTAL2)
V
OH
, Output High Voltage
2
V
DD
– 0.6 V min V
DD
= 3 V, I
SOURCE
= 100 mA
V
OL
, Output Low Voltage
2
0.4 V max V
DD
= 3 V, I
SINK
= 100 mA
V
OH
, Output High Voltage
2
4V minV
DD
= 5 V, I
SOURCE
= 200 mA
V
OL
, Output Low Voltage
2
0.4 V max V
DD
= 5 V, I
SINK
= 1.6 mA
Floating-State Leakage Current ± 10 mA max
Floating-State Output Capacitance ± 10 pF typ
Data Output Coding Offset Binary
START-UP TIME
From Power-On 300 ms typ
POWER REQUIREMENTS
Power Supply Voltage
V
DD
– GND 2.7/3.6 V min/V max V
DD
= 3 V nom
4.75/5.25 V min/V max V
DD
= 5 V nom
Power Supply Currents
I
DD
Current (Normal Mode)
4
1.5 mA max V
DD
= 3 V, 1.3 mA typ
1.7 mA max V
DD
= 5 V, 1.5 mA typ
I
DD
(Power-Down Mode, CS = 1) 9 mA max V
DD
= 3 V, 6 mA typ
24 mA max V
DD
= 5 V, 20 mA typ
NOTES
1
Temperature range –40∞C to +85∞C.
2
Guaranteed by design and/or characterization data on production release.
3
When a 28.8 kHz crystal is used, normal-mode rejection is improved so that the rejection equals 75 dB at 50 Hz ± 1 Hz and equals 66 dB at 60 Hz ± 1 Hz.
4
Normal mode refers to the case where the ADC is running.
Specifications subject to change without notice.
REV. C
–4–
AD7783
Limit at T
MIN
, T
MAX
Parameter (B Version) Unit Conditions/Comments
t
1
30.5176 ms typ Crystal Oscillator Period
t
ADC
50.54 ms typ 19.79 Hz Update Rate
t
2
0 ns min CS Falling Edge to DOUT Active
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
3
2 ¥ t
ADC
ns typ Channel Settling Time
t
4
3
0 ns min SCLK Active Edge to Data Valid Delay
4
60 ns max V
DD
= 4.75 V to 5.25 V
80 ns max V
DD
= 2.7 V to 3.6 V
t
7
5
10 ns min Bus Relinquish Time after CS Inactive Edge
80 ns max
t
8
0 ns min CS Rising Edge to SCLK Inactive Edge Hold Time
t
9
10 ns min SCLK Inactive to DOUT High
80 ns max
Slave Mode Timing
t
5
100 ns min SCLK High Pulse Width
t
6
100 ns min SCLK Low Pulse Width
Master Mode Timing
t
5
t
1
/2 ms typ SCLK High Pulse Width
t
6
t
1
/2 ms typ SCLK Low Pulse Width
t
10
t
1
/2 ms min DOUT Low to First SCLK Active Edge
4
3t
1
/2 ms max
NOTES
1
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 2.
3
These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means the times quoted in the timing characteristics are the true bus relin-
quish times of the part and as such are independent of external bus loading capacitances.
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.7 V to 3.6 V or V
DD
= 4.75 V to 5.25 V; GND = 0 V; XTAL = 32.768 kHz;
Input Logic 0 = 0 V, Logic 1 = V
DD
, unless otherwise noted.)
TO OUTPUT
PIN
50pF
I
SINK
(1.6mA WITH V
DD
= 5V
100␮A WITH V
DD
= 3V)
1.6V
I
SOURCE
( 200␮A WITH V
DD
= 5V
100␮A WITH V
DD
= 3V)
Figure 1. Load Circuit for Timing Characterization
REV. C
AD7783
–5–
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25∞C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to V
DD
+ 0.3 V
Total AIN/REFIN Current (Indefinite) . . . . . . . . . . . . . 30 mA
Digital Input Voltage to GND . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
TSSOP Package
␪
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 97.9∞C/W
␪
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 14∞C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause per-
manent damage to the device. This is a stress rating only; functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CS (I)
DOUT/RDY (O)
SLAVE MODE
SCLK (I)
MASTER MODE
SCLK (O)
I = INPUT TO AD7783, AND O = OUTPUT FROM AD7783.
SLAVE MODE IS SELECTED BY TYING THE MODE PIN
+,*+, WHILE MASTER MODE IS SELECTED BY TYING THE MODE PIN /2:.
t
2
t
3
t
4
t
5
t
6
t
4
t
10
t
5
t
6
t
8
t
7
t
9
MSB
MSB
LSB LSB
Figure 2. Slave/Master Mode Timing Diagram
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7783 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
P1-P3P4-P6P7-P9P10-P12P13-P13

AD7783BRUZ-REEL7

Mfr. #:
Buy AD7783BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Pin-Config 24-bit w/ Excitation Crnt Src
Lifecycle:
New from this manufacturer.
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