LTC3416
12
3416fa
APPLICATIO S I FOR ATIO
WUUU
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics curves. Thus, to obtain I
2
R losses, simply add R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
In most applications, the LTC3416 does not dissipate
much heat due to its high efficiency. But in applications
where the LTC3416 is running at high ambient tempera-
ture with low supply voltage and high duty cycles, such as
in dropout, the heat dissipated may exceed the maximum
junction temperature of the part. If the junction tempera-
ture reaches approximately 150°C, both power switches
will be turned off and the SW node will become high
impedance.
To avoid the LTC3416 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the θ
JA
is 38°C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3416, the
Exposed Pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in figure 1a will provide adequate compensation
for most applications.
Design Example
As a design example, consider using the LTC3416 in an
application with the following specifications: V
IN
= 3.3V,
V
OUT1
= 1.8V, V
OUT2
= 2.5V, I
OUT1(MAX)
= I
OUT2(MAX)
= 4A,
f = 1MHz. V
OUT1
and V
OUT2
must track when powering up
and powering down.
First, calculate the timing resistor:
Rkk
OSC
==
308 10
110
10 298
11
6
.•
•
–
Use a standard value of 294kΩ. Next, calculate the induc-
tor values for about 40% ripple current:
L
V
MHz A
V
V
H
L
V
MHz A
V
V
H
1
18
116
1
18
33
051
2
25
116
1
25
33
038
=
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
=µ
=
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
=µ
.
•.
–
.
.
.
.
•.
–
.
.
.
Using a 0.47µH inductor for both results in maximum
ripple currents of:
∆ =
µ
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
=
∆ =
µ
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
=
I
V
MHz H
V
V
A
I
V
MHz H
V
V
A
L
L
1
2
18
1047
1
18
33
174
25
1047
1
25
33
129
.
•.
–
.
.
.
.
•.
–
.
.
.
C
OUT1
and C
OUT2
will be selected based on the ESR that is
required to satisfy the output voltage ripple requirement
and the bulk capacitance needed for loop stability. For this
design, two 100µF ceramic capacitors will be used at each
output.
