DS1722
TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 12
*SCLK can be either polarity, timing shown for CPOL = 1.
NOTES:
1. All voltages are referenced to ground.
2. Logic 0 voltages are specified at a sink current of 3 mA.
3. Logic 1 voltages are specified at a source current of 1 mA.
4. I
13 of 14
CC
specified with SCLK=V and CE=GND. Typical I is 0.25 µA and I
DDD CC1 CC
is 0.3 mA at 25°C
and V
DDD =
2.65V
.
5. Measured at V =0.7 V or V
IH DDD IL
=0.2 V and 10 ms maximum rise and fall time.
DDD
6. Measured with 50 pF load
7. Measured at V =0.7 V or V
OH DDD OL
=0.2 V . Measured from the 50% point of SCLK to the V
DDD OH
minimum of SDO.
