MAX1247BCEE Datasheet MAX1246AEEE+, MAX1246BCEE+T, MAX1247BEEE+T | P10-P12

MAX1246/MAX1247

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

10 ______________________________________________________________________________________

_______________Detailed Description

The MAX1246/MAX1247 analog-to-digital converters

(ADCs) use a successive-approximation conversion

technique and input track/hold (T/H) circuitry to convert

an analog signal to a 12-bit digital output. A flexible seri-

al interface provides easy interface to microprocessors

(µPs). Figure 3 is a block diagram of the MAX1246/

MAX1247.

Pseudo-Differential Input

The sampling architecture of the ADC’s analog com-

parator is illustrated in the equivalent input circuit

(Figure 4). In single-ended mode, IN+ is internally

switched to CH0–CH3, and IN- is switched to COM. In

differential mode, IN+ and IN- are selected from two

pairs: CH0/CH1 and CH2/CH3. Configure the channels

with Tables 2 and 3. Please note that the codes for

CH0–CH3 in the MAX1246/MAX1247 correspond to the

codes for CH2–CH5 in the eight-channel (MAX146/

MAX147) versions.

In differential mode, IN- and IN+ are internally switched

to either of the analog inputs. This configuration is

pseudo-differential to the effect that only the signal at IN+

is sampled. The return side (IN-) must remain stable within

±0.5LSB (±0.1LSB for best results) with respect to AGND

during a conversion. To accomplish this, connect a 0.1µF

capacitor from IN- (the selected analog input) to AGND.

During the acquisition interval, the channel selected

as the positive input (IN+) charges capacitor C

HOLD

The acquisition interval spans three SCLK cycles and

ends on the falling SCLK edge after the last bit of the

input control word has been entered. At the end of the

acquisition interval, the T/H switch opens, retaining

charge on C

HOLD

as a sample of the signal at IN+.

The conversion interval begins with the input multiplexer

switching C

HOLD

from the positive input (IN+) to the

negative input (IN-). In single-ended mode, IN- is simply

COM. This unbalances node ZERO at the comparator’s

input. The capacitive DAC adjusts during the remainder

of the conversion cycle to restore node ZERO to 0V

within the limits of 12-bit resolution. This action is equiv-

alent to transferring a 16pF x [(V

) - (V

-)] charge

from C

HOLD

to the binary-weighted capacitive DAC,

which in turn forms a digital representation of the analog

input signal.

Track/Hold

The T/H enters its tracking mode on the falling clock

edge after the fifth bit of the 8-bit control word has been

shifted in. It enters its hold mode on the falling clock

edge after the eighth bit of the control word has been

shifted in. If the converter is set up for single-ended

inputs, IN- is connected to COM, and the converter

samples the “+” input. If the converter is set up for dif-

ferential inputs, IN- connects to the “-” input, and the

difference of |IN+ - IN-

| is sampled. At the end of the

conversion, the positive input connects back to IN+,

and C

HOLD

charges to the input signal.

The time required for the T/H to acquire an input signal

is a function of how quickly its input capacitance is

charged. If the input signal’s source impedance is high,

the acquisition time lengthens, and more time must be

INPUT

SHIFT

CONTROL

LOGIC

INT

CLOCK

OUTPUT

SHIFT

+1.21V

REFERENCE

(MAX1246)

T/H

ANALOG

INPUT

MUX

12-BIT

SAR

ADC

DOUT

SSTRB

DGND

AGND

SCLK

DIN

COM

REFADJ

VREF

OUT

REF

CLOCK

+2.500V

20kΩ

*A ≈ 2.00 (MAX1247)

CH3

CH2

CH1

CH0

MAX1246

MAX1247

SHDN

≈ 2.06*

Figure 3. Block Diagram

CH0

CH1

CH2

CH3

COM

SWITCH

TRACK

T/H

SWITCH

9kΩ

HOLD

12-BIT CAPACITIVE DAC

VREF

ZERO

COMPARATOR

–

16pF

SINGLE-ENDED MODE: IN+ = CH0–CH3, IN- = COM.

DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF

CH0/CH1 AND CH2/CH3.

AT THE SAMPLING INSTANT,

THE MUX INPUT SWITCHES

FROM THE SELECTED IN+

CHANNEL TO THE SELECTED

IN- CHANNEL.

INPUT

MUX

Figure 4. Equivalent Input Circuit

MAX1246/MAX1247

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

______________________________________________________________________________________ 11

BIT NAME DESCRIPTION

7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.

6 SEL2 These three bits select which of the four channels are used for the conversion (Tables 2 and 3).

5 SEL1

4 SEL0

3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an

analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range

from -VREF / 2 to +VREF / 2.

2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-

ended mode, input signal voltages are referred to COM. In differential mode, the voltage

difference between two channels is measured (Tables 2 and 3).

1 PD1 Selects clock and power-down modes.

0(LSB) PD0 PD1 PD0 Mode

0 0 Full power-down

0 1 Fast power-down

1 0 Internal clock mode

1 1 External clock mode

Table 1. Control-Byte Format

allowed between conversions. The acquisition time,

ACQ

, is the maximum time the device takes to acquire

the signal, and is also the minimum time needed for the

signal to be acquired. It is calculated by the following

equation:

ACQ

= 9 x (R

+ R

) x 16pF

where R

= 9kΩ, R

= the source impedance of the

input signal, and t

ACQ

is never less than 1.5µs. Note

that source impedances below 1kΩ do not significantly

affect the ADC’s AC performance.

Higher source impedances can be used if a 0.01µF

capacitor is connected to the individual analog inputs.

Note that the input capacitor forms an RC filter with the

input source impedance, limiting the ADC’s signal

bandwidth.

Input Bandwidth

The ADC’s input tracking circuitry has a 2.25MHz

small-signal bandwidth, so it is possible to digitize

high-speed transient events and measure periodic sig-

nals with bandwidths exceeding the ADC’s sampling

rate by using undersampling techniques. To avoid

high-frequency signals being aliased into the frequency

band of interest, anti-alias filtering is recommended.

Analog Input Protection

Internal protection diodes, which clamp the analog input

to V

and AGND, allow the channel input pins to swing

from AGND - 0.3V to V

+ 0.3V without damage.

However, for accurate conversions near full scale, the

inputs must not exceed V

by more than 50mV or be

lower than AGND by 50mV.

If the analog input exceeds 50mV beyond the sup-

plies, do not forward bias the protection diodes of

off channels over 4mA.

How to Start a Conversion

Start a conversion by clocking a control byte into DIN.

With CS low, each rising edge on SCLK clocks a bit from

DIN into the MAX1246/MAX1247’s internal shift register.

After CS falls, the first arriving logic “1” bit defines the

control byte’s MSB. Until this first “start” bit arrives, any

number of logic “0” bits can be clocked into DIN with no

effect. Table 1 shows the control-byte format.

The MAX1246/MAX1247 are compatible with SPI™/

QSPI™ and Microwire™ devices. For SPI, select the

correct clock polarity and sampling edge in the SPI

control registers: set CPOL = 0 and CPHA = 0. Micro-

wire, SPI, and QSPI all transmit a byte and receive a

byte at the same time. Using the Typical Operating

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

(MSB) (LSB)

START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0

MAX1246/MAX1247

+2.7V, Low-Power, 4-Channel,

Serial 12-Bit ADCs in QSOP-16

12 ______________________________________________________________________________________

Circuit, the simplest software interface requires only

three 8-bit transfers to perform a conversion (one 8-bit

transfer to configure the ADC, and two more 8-bit trans-

fers to clock out the 12-bit conversion result). See Figure

19 for MAX1246/MAX1247 QSPI connections.

Simple Software Interface

Make sure the CPU’s serial interface runs in master

mode so the CPU generates the serial clock. Choose a

clock frequency from 100kHz to 2MHz.

1) Set up the control byte for external clock mode and

call it TB1. TB1 should be of the format: 1XXXXX11

binary, where the Xs denote the particular channel

and conversion mode selected.

2) Use a general-purpose I/O line on the CPU to pull

CS low.

3) Transmit TB1 and, simultaneously, receive a byte

and call it RB1. Ignore RB1.

4) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB2.

5) Transmit a byte of all zeros ($00 hex) and, simulta-

neously, receive byte RB3.

6) Pull CS high.

Figure 5 shows the timing for this sequence. Bytes RB2

and RB3 contain the result of the conversion, padded

with one leading zero and three trailing zeros. The total

conversion time is a function of the serial-clock fre-

quency and the amount of idle time between 8-bit

transfers. To avoid excessive T/H droop, make sure the

total conversion time does not exceed 120µs.

Digital Output

In unipolar input mode, the output is straight binary

(Figure 16). For bipolar inputs, the output is two’s com-

plement (Figure 17). Data is clocked out at the falling

edge of SCLK in MSB-first format.

Clock Modes

The MAX1246/MAX1247 may use either an external

serial clock or the internal clock to perform the succes-

sive-approximation conversion. In both clock modes,

the external clock shifts data in and out of the

MAX1246/MAX1247. The T/H acquires the input signal

as the last three bits of the control byte are clocked into

DIN. Bits PD1 and PD0 of the control byte program the

clock mode. Figures 6–9 show the timing characteristics

common to both modes.

External Clock

In external clock mode, the external clock not only shifts

data in and out, but it also drives the analog-to-digital

conversion steps. SSTRB pulses high for one clock

period after the last bit of the control byte. Succes-

sive-approximation bit decisions are made and appear

at DOUT on each of the next 12 SCLK falling edges

(Figure 5). SSTRB and DOUT go into a high-impedance

state when CS goes high; after the next CS falling edge,

SSTRB outputs a logic low. Figure 7 shows the SSTRB

timing in external clock mode.

The conversion must complete in some minimum time,

or droop on the sample-and-hold capacitors may

degrade conversion results. Use internal clock mode if

the serial clock frequency is less than 100kHz, or if

serial clock interruptions could cause the conversion

interval to exceed 120µs.

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 COM

00 1+ –

10 1 + –

01 0 + –

11 0 + –

Table 2. Channel Selection in Single-Ended Mode (SGL/

DDIIFF

= 1)

SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3

00 1+ –

01 0 + –

10 1– +

11 0 – +

Table 3. Channel Selection in Differential Mode (SGL/

DDIIFF

= 0)

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MAX1247BCEE

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Analog to Digital Converters - ADC +2.7V, Low-Power, 4-Channel, Serial 12-Bit ADCs in QSOP-16

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