ADuM3400/ADuM3401/ADuM3402 Data Sheet
Rev. E | Page 10 of 24
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
BRW Package
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
15 35 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
PHL
4
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
CRW Package
Minimum Pulse Width
2
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 30 40 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
14 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
f
C
L
= 15 pF, CMOS signal levels
5 V/3.3 V Operation 3.0 ns
3.3 V/5 V Operation 2.5 ns
Common-Mode Transient Immunity
7
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
L
Ix
CM
transient magnitude = 800 V