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IS62WV25616DALL-55TI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Integrated Silicon Solution, Inc. — www.issi.com 7
Rev. D1
3/10/2015
IS62WV25616DALL/DBLL, IS65WV25616DBLL
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(OverOperatingRange)
35 ns 45 ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trC ReadCycleTime 35 — 45 — 55 — ns
taa AddressAccessTime — 35 — 45 — 55 ns
tOHa OutputHoldTime 10 — 10 — 10 — ns
taCs1/taCs2 CS1/CS2AccessTime — 35 — 45 — 55 ns
tdOe OEAccessTime — 10 — 20 — 25 ns
tHzOe
(2)
OEtoHigh-ZOutput 0 10 0 15 0 20 ns
tLzOe
(2)
OEtoLow-ZOutput 3 — 5 — 5 — ns
tHzCs1/tHzCs2
(2)
CS1/CS2toHigh-ZOutput 0 10 0 15 0 20 ns
tLzCs1/tLzCs2
(2)
CS1/CS2toLow-ZOutput 5 — 5 — 10 — ns
tba LB, UBAccessTime — 35 — 45 — 55 ns
tHzb LB, UBtoHigh-ZOutput 0 15 0 15 0 20 ns
tLzb LB, UBtoLow-ZOutput 0 — 0 — 0 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4to
V
dd-0.2V/Vdd-0.3VandoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
IS62WV25616DALL/DBLL, IS65WV25616DBLL
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. D1
3/10/2015
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
(Address Controlled) (CS1 = OE = ViL, CS2 = WE = ViH, UB or LB = ViL)
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACE1/
t
ACE2
t
LZCE1/
t
LZCE2
t
HZOE
HIGH-Z
DATA VALID
t
HZCS1/
t
HZCS2
ADDRESS
OE
CS1
CS2
DOUT
LB, UB
t
HZB
t
BA
t
LZB
AC WAVEFORMS
READ CYCLE NO. 2
(1,3)
(CS1, CS2, OE, AND UB/LB Controlled)
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CS1, UB, or LB =
ViL. Cs2=WE=ViH.
3. Address is valid prior to or coincident with CS1LOWtransition.
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. D1
3/10/2015
IS62WV25616DALL/DBLL, IS65WV25616DBLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(OverOperatingRange)
35 ns 45 ns 55 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
twC WriteCycleTime 35 — 45 — 55 — ns
tsCs1/tsCs2 CS1/CS2toWriteEnd 25 — 35 — 45 — ns
taw AddressSetupTimetoWriteEnd 25 — 35 — 45 — ns
tHa AddressHoldfromWriteEnd 0 — 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — 0 — ns
tPwb LB, UBValidtoEndofWrite 25 — 35 — 45 — ns
tPwe WEPulseWidth 25 — 35 — 40 — ns
tsd DataSetuptoWriteEnd 20 — 20 — 25 — ns
tHd DataHoldfromWriteEnd 0 — 0 — 0 — ns
tHzwe
(3)
WELOWtoHigh-ZOutput — 10 — 20 — 20 ns
tLzwe
(3)
WEHIGHtoLow-ZOutput 3 — 5 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof0.4Vto
V
dd-0.2V/Vdd-0.3VandoutputloadingspeciedinFigure1.
2.
TheinternalwritetimeisdenedbytheoverlapofCS1LOW,CS2HIGHandUB or LB, and WELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,but
any one can go inactive to
terminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfallingedgeofthesignalthatterminatesthe
write.
3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

IS62WV25616DALL-55TI

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IC SRAM 4M PARALLEL 44TSOP II
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