DS802 April 24, 2012 www.xilinx.com 1
Product Specification
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Introduction
The Xilinx LogiCORE™ IP DisplayPort™ interconnect
protocol is designed for transmission and reception of
serial-digital video for consumer and professional
displays. DisplayPort is a high-speed serial interface
standard supported by PC chipsets, GPU’s and display
controllers, HDTV and monitors from industry leaders
and major silicon manufacturers.
This protocol replaces VGA, DVI and HDMI™ outside
and LVDS inside the box for higher resolution, higher
frame rate and color bit depth display.
DisplayPort IP can support standard rates of 1.62 Gb/s,
2.7 Gb/s and 5.4 Gb/s for consumer and professional
displays. When used in high-performance 7 series
devices, the DisplayPort core can transmit and receive
at 5.4 Gb/s.
The Xilinx DisplayPort IP core is designed to the Video
Electronics Standards Association (VESA) DisplayPort
Standard v1.1a and DisplayPort Standard v1.2
specifications [Ref 1][Ref 2].
Features
• Source (TX) and Sink (RX) Controllers
• Designed to VESA DisplayPort Standard v1.1a and
v1.2
• For a 5.4 Gb/s link rate, a high performance
FPGA is required with speed grade -2 or -3
• DisplayPort v1.2 is supported with 7 series
devices
• One, two or four pixel-wide video interface
supporting up to a 4k x 2k monitor resolution
• 1, 2 or 4 lanes at 1.62, 2.7 or 5.4 Gb/s
• RGB and YCbCr color space, up to 16 bits per color
• Auto lane rate and width negotiation
• I2C over a 1 Mb/s AUX channel
• Secondary channel audio support (2-channel)
• With additional license, supports DisplayPort
Audio Support (two-channel with SPDIF). See
product page
for details.
LogiCORE IP DisplayPort v3.1
DS802 April 24, 2012 Product Specification
LogiCORE IP Facts
Core Specifics
Supported
Device
Family
(1)
1. For a complete listing of supported devices, see the release notes
for this core.
Virtex-7, Kintex-7,
Virtex-6, Spartan-6
Supported
User Interfaces
Native Video, AXI4-Stream, AXI4-Lite
Resources Used
I/O
(to pins)
LUTs FFs
Block
RAMs
Sink 12 ~7000 ~5400 0
Source 13 ~6500 ~5100 0
Provided with Core
Documentation
Product Specification
User Guide
Design File
Formats
Verilog and VHDL
NGC Netlist
Scripts for Unix and Windows
Constraints File
.ucf (user constraints file)
Full Timing Constraints
Transceiver Physical Constraints
Verification Verilog Test Bench
Instantiation
Template
Verilog and VHDL Wrapper
Example
Design
Simple RTL Source Policy Maker
RTL Sink Policy Maker
RTL EDID ROM, RTL I2C Controller
Demonstration Test Bench
Design Tool Requirements
Xilinx
Implementation
Tools
ISE 14.1, Vivado 2012.1
Verification
(2)
2. For the supported versions of the tools, see the ISE Design Suite
14: Release Notes Guide.
Mentor Graphics ModelSim
Cadence Incisive Enterprise Simulator
Simulation
(2)
Xilinx Synthesis Technology (XST)
Synthesis Xilinx XST
Support
Provided by Xilinx, Inc.
