M41ST84Y, M41ST84W
20/31
Power-fail INPUT/OUTPUT
The Power-Fail Input (PFI) is compared to an in-
ternal reference voltage (1.25V). If PFI is less than
the power-fail threshold (V
PFI
), the Power-Fail
Output (PFO)
will go low. This function is intended
for use as an under-voltage detector to signal a
failing power supply. Typically PFI is connected
through an external voltage divider (see Figure
7., page 6) to either the unregulated DC input (if it
is available) or the regulated output of the V
CC
reg-
ulator. The voltage divider can be set up such that
the voltage at PFI falls below V
PFI
several millisec-
onds before the regulated V
CC
input to the
M41ST84Y/W or the microprocessor drops below
the minimum operating voltage.
During battery back-up, the power-fail comparator
turns off and PFO
goes (or remains) low. This oc-
curs after V
CC
drops below V
PFD
(min). When pow-
er returns, PFO
is forced high, irrespective of V
PFI
for the write protect time (t
REC
), which is the time
from V
PFD
(max) until the inputs are recognized. At
the end of this time, the power-fail comparator is
enabled and PFO
follows PFI. If the comparator is
unused, PFI should be connected to V
SS
and PFO
left unconnected.
Century Bit
Bits D7 and D6 of Clock Register 03h contain the
CENTURY ENABLE Bit (CEB) and the CENTURY
Bit (CB). Setting CEB to a “1” will cause CB to tog-
gle, either from a “0” to “1” or from “1” to “0” at the
turn of the century (depending upon its initial
state). If CEB is set to a “0”, CB will not toggle.
Output Driver Pin
When the FT Bit, AFE Bit and watchdog register
are not set, the IRQ
/FT/OUT pin becomes an out-
put driver that reflects the contents of D7 of the
Control Register. In other words, when D7 (OUT
Bit) and D6 (FT Bit) of address location 08h are a
'0,' then the IRQ
/FT/OUT pin will be driven low.
Note: The IRQ
/FT/OUT pin is an open drain which
requires an external pull-up resistor.
Battery Low Warning
The M41ST84Y/W automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0Fh, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
CC
is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT top
may be replaced while V
CC
is applied to the de-
vice.
Note: This will cause the clock to lose time during
the interval the SNAPHAT battery/crystal top is
disconnected.
The M41ST84Y/W only monitors the battery when
a nominal V
CC
is applied to the device. Thus appli-
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
t
REC
Bit
Bit D7 of Clock Register 04h contains the t
REC
Bit
(TR). t
REC
refers to the automatic continuation of
the deselect time after V
CC
reaches V
PFD
. This al-
lows for a voltage setting time before WRITEs may
again be performed to the device after a power-
down condition. The t
REC
Bit will allow the user to
set the length of this deselect time as defined by
Table 7., page 21.
Initial Power-on Defaults
Upon initial application of power to the device, the
following register bits are set to a '0' state: Watch-
dog Register, TR, FT, AFE, ABE, and SQWE. The
following bits are set to a '1' state: ST, OUT, and
HT (see Table 8., page 21).
