25
LTC1417
sn1417 1417fas
* (This assumes an E-Clock frequency of 4MHz. For higher
* E-Clock frequencies, change the above value of $50 to a
* value that ensures the SCK frequency is 2MHz or less.)
GETDATAPSHX
PSHY
PSHA
*
*****************************************
* Setup indecies *
*****************************************
*
LDX #$0 The X register is used as a pointer to the memory
* locations that hold the conversion data
LDY #$1000
*
*****************************************
* The next short loop ensures that the *
* LTC1417’s conversion is finished *
* before starting the SPI data transfer *
*****************************************
*
CONVENDLDAA PORTC Retrieve the contents of port D
ANDA #%10000000 Look at Bit7
* Bit7 = Hi; the LTC1417’s conversion is complete
* Bit7 = Lo; the LTC1417’s conversion is not
* complete
BPL CONVEND Branch to the loop’s beginning while Bit7 remains
* low
*
*************************************************************************
* This routine sends data to the LTC1417 and sets its MUX channel. The *
* very first time this routine is entered produces invalid data. Each *
* time thereafter, the data will correspond to the previous active *
* CONVST signal sent to the LTC1417. *
*************************************************************************
*
LDAA #$00 Dummy value for upper byte of 16-bit SPI transfer
BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic
* low, selecting the LTC1417
STAA SPDR Transfer Accum. A contents to SPI register to initiate
* serial transfer
WAITMX1 LDAA SPSR Get SPI transfer status
BPL WAITMX1If the transfer is not finished, read status
LDAA SPDR Load accumulator A with the current byte of LTC1417 data
* that was just received
STAA DIN1 Transfer the LTC1417’s high byte (Bit13 - Bit6) to memory
LDAA MUX Retrieve MUX address
ORAA #$08 Set the MUX’s ENABLE bit
STAA SPDR Transfer Accum. A contents to SPI register to initiate
* serial transfer
WAITMX2 LDAA SPSR Get SPI transfer status
BPL WAITMX2If the transfer is not finished, read status
BSET PORTD,Y %00100000 This sets the SS* output bit to a logic
* high, de-selecting the LTC1417
LDAA SPDR Load accumulator A with the current byte of LTC1417 data
* that was just received
STAA DIN2 Transfer the LTC1417’s low byte (Bit5 - Bit0) to memory
LDD DIN1 Load the contents of DIN1 and DIN2 into the double
* accumulator D
LSRD
LSRD Two logical shifts to the right to right justify the
* 14-bit conversion results
STD DIN1 Place right justified result back in memory
TYPICAL APPLICATIONS
U
