AD5362BSTZ Datasheet AD5362BSTZ, AD5363BSTZ, AD5362BSTZ-REEL | P1-P3

8-Channel, 16-/14-Bit,

Serial Input, Voltage Output DAC

AD5362/AD5363

Rev. A

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FEATURES

8-channel DAC in 52-lead LQFP and 56-lead LFCSP packages

Guaranteed monotonic to 16/14 bits

Nominal output voltage range of −10 V to +10 V

Multiple output voltage spans available

Thermal shutdown function

Channel monitoring multiplexer

GPIO function

System calibration function allowing user-programmable

offset and gain

Channel grouping and addressing features

Data error checking feature

SPI-compatible serial interface

2.5 V to 5.5 V digital interface

Digital reset (

RESET

)

Clear function to user-defined SIGGNDx

Simultaneous update of DAC outputs

APPLICATIONS

Instrumentation

Industrial control systems

Level setting in automatic test equipment (ATE)

Variable optical attenuators (VOA)

Optical line cards

FUNCTIONAL BLOCK DIAGRAM

SERIAL

INTERFACE

SDI

SCLK

SDO

SYNC

BUSY

RESET

CLR

STATE

MACHINE

CONTROL

GPIO

MON_OUT

MON_IN1

MON_IN0

PEC

TEMP_OUT

BIN/2SCOMP

TEMP

SENSOR

AD5362/

AD5363

n = 16 FOR AD5362

n = 14 FOR AD5363

A/B SELECT

MUX 2s

DAC 4

OFS0

OFFSET

DAC 0

OFFSET

DAC 1

DAC 4

BUFFER

GROUP 0

GROUP 1

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

VREF0

VOUT0

VOUT1

VOUT2

VOUT4

VOUT5

VOUT6

VOUT7

VOUT3

SIGGND0

SIGGND1

VREF1

X1 REGISTER

M REGISTER

C REGISTER

MUX

AGND DGND LDAC

MUX

VOUT0 TO

VOUT7

A/B

MUX

X2A REGISTER

X2B REGISTER

A/B SELECT

MUX 2s

DAC 0

X1 REGISTER

M REGISTER

C REGISTER

MUX

A/B

MUX

X2A REGISTER

X2B REGISTER

DAC 7

X1 REGISTER

M REGISTER

C REGISTER

MUX

A/B

MUX

X2A REGISTER

X2B REGISTER

DAC 3

X1 REGISTER

M REGISTER

C REGISTER

MUX

A/B

MUX

X2A REGISTER

X2B REGISTER

OFS1

05762-001

Figure 1.

AD5362/AD5363

Rev. A | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

AC Characteristics ........................................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings .......................................................... 10

ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11

Typical Performance Characteristics ........................................... 13

Terminology .................................................................................... 15

Theory of Operation ...................................................................... 16

DAC Architecture ....................................................................... 16

Channel Groups .......................................................................... 16

A/B Registers and Gain/Offset Adjustment ............................ 17

Offset DACs ................................................................................ 17

Output Amplifier ........................................................................ 18

Transfer Function ....................................................................... 18

Reference Selection .................................................................... 18

Calibration ................................................................................... 19

Additional Calibration ............................................................... 19

Reset Function ............................................................................ 20

Clear Function ............................................................................ 20

BUSY

and

LDAC

Functions...................................................... 20

BIN

/2SCOMP Pin ...................................................................... 20

Temperature Sensor ................................................................... 20

Monitor Function ....................................................................... 21

GPIO Pin ..................................................................................... 21

Power-Down Mode .................................................................... 21

Thermal Shutdown Function ................................................... 21

Toggle Mode ................................................................................ 21

Serial Interface ................................................................................ 22

SPI Write Mode .......................................................................... 22

SPI Readback Mode ................................................................... 22

Packet Error Checking ............................................................... 23

Channel Addressing and Special Modes ................................. 23

Special Function Mode .............................................................. 24

Applications Information .............................................................. 26

Power Supply Decoupling ......................................................... 26

Power Supply Sequencing ......................................................... 26

Interfacing Examples ................................................................. 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 28

REVISION HISTORY

3/08—Rev. 0 to Rev. A

Added 56-Lead LFCSP_VQ .............................................. Universal

Changes to Table 2 ............................................................................ 4

Added t

Parameter ......................................................................... 7

Changes to Figure 4 .......................................................................... 8

Changes to Table 6 .......................................................................... 11

Changes to A/B Registers and Gain/Offset Adjustment

Section .............................................................................................. 17

Changes to Calibration Section .................................................... 19

Changes to Reset Function Section and

BUSY

and

LDAC

Functions Section ........................................................................... 20

Changes to Channel Addressing and Special Modes Section .. 23

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 28

1/08—Revision 0: Initial Version

AD5362/AD5363

Rev. A | Page 3 of 28

GENERAL DESCRIPTION

The AD5362/AD5363 contain eight 16-/14-bit DACs in a single

52-lead LQFP package or 56-lead LFCSP package. The devices

provide buffered voltage outputs with a span of 4× the reference

voltage. The gain and offset of each DAC can be independently

trimmed to remove errors. For even greater flexibility, the device

is divided into two groups of four DACs, and the output range

of each group can be independently adjusted by an offset DAC.

The AD5362/AD5363 offer guaranteed operation over a wide

supply range with V

from −16.5 V to −4.5 V and V

from 8 V

to 16.5 V. The output amplifier headroom requirement is 1.4 V,

operating with a load current of 1 mA.

The AD5362/AD5363 have a high speed 4-wire serial interface

that is compatible with SPI, QSPI™, MICROWIRE™, and DSP

interface standards and can handle clock speeds of up to

50 MHz. All the outputs can be updated simultaneously by

taking the

LDAC

input low. Each channel has a programmable

gain and an offset adjust register.

Each DAC output is gained and buffered on chip with respect

to an external SIGGNDx input. The DAC outputs can also be

switched to SIGGNDx via the

CLR

pin.

Table 1. High Channel Count Bipolar DACs

Model Resolution (Bits) Nominal Output Span Output Channels Linearity Error (LSB)

AD5360 16 4 × V

REF

(20 V) 16 ±4

AD5361 14 4 × V

REF

(20 V) 16 ±1

AD5362 16 4 × V

REF

(20 V) 8 ±4

AD5363 14 4 × V

REF

(20 V) 8 ±1

AD5370 16 4 × V

REF

(12 V) 40 ±4

AD5371 14 4 × V

REF

(12 V) 40 ±1

AD5372 16 4 × V

REF

(12 V) 32 ±4

AD5373 14 4 × V

REF

(12 V) 32 ±1

AD5378 14 ±8.75 V 32 ±3

AD5379 14 ±8.75 V 40 ±3

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

AD5362BSTZ

Mfr. #:

Buy AD5362BSTZ

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 8-CH 16-bit Serial bipolar IC

Lifecycle:

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AD5362BSTZ

AD5362BSTZ

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