LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 58 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
11.1 Internal oscillators
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
11.2 I/O pins
[1] Applies to standard I/O pins and RESET pin.
11.3 USB interface
[1] Characterized but not implemented as production test. Guaranteed by design.
Table 11. Dynamic characteristic: internal oscillators
T
amb
= 40 C to +85 C; 3.0 V V
DD(3V3)
3.6 V.
[1]
Symbol Parameter Conditions Min Typ
[2]
Max Unit
f
osc(RC)
internal RC oscillator frequency - 3.96 4.02 4.04 MHz
f
i(RTC)
RTC input frequency - - 32.768 - kHz
Table 12. Dynamic characteristic: I/O pins
[1]
T
amb
= 40 C to +85 C; V
DD(3V3)
over specified ranges.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time pin configured as output 3.0 - 5.0 ns
t
f
fall time pin configured as output 2.5 - 5.0 ns
Table 13. Dynamic characteristics of USB pins (full-speed)
C
L
= 50 pF; R
pu
= 1.5 k
on D+ to V
DD(3V3)
,unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
t
r
rise time 10 % to 90 % 8.5 - 13.8 ns
t
f
fall time 10 % to 90 % 7.7 - 13.7 ns
t
FRFM
differential rise and fall time
matching
t
r
/t
f
--109%
V
CRS
output signal crossover voltage 1.3 - 2.0 V
t
FEOPT
source SE0 interval of EOP see Figure 16 160 - 175 ns
t
FDEOP
source jitter for differential transition
to SE0 transition
see Figure 16 2-+5ns
t
JR1
receiver jitter to next transition 18.5 - +18.5 ns
t
JR2
receiver jitter for paired transitions 10 % to 90 % 9-+9ns
t
EOPR1
EOP width at receiver must reject as
EOP; see
Figure 16
[1]
40 --ns
t
EOPR2
EOP width at receiver must accept as
EOP; see
Figure 16
[1]
82 --ns
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 59 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
11.4 Static external memory interface
Table 14. Dynamic characteristics: Static external memory interface
C
L
=30pF, T
amb
=
40
C to 85
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.0 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
Common to read and write cycles
[1]
t
CSLAV
CS LOW to address valid
time
0.29 0.20 2.54 ns
Read cycle parameters
[1][2]
t
OELAV
OE LOW to address valid
time
0.29 0.20 2.54 ns
t
CSLOEL
CS LOW to OE LOW time 0.78 + T
cy(CCLK)
WAITOEN 0 + T
cy(CCLK)
WAITOEN 0.49 + T
cy(CCLK)
WAITOEN ns
t
am
memory access time
[3][4]
(WAITRD WAITOEN + 1)
T
cy(CCLK)
12.70
(WAITRD WAITOEN + 1)
T
cy(CCLK)
9.57
(WAITRD WAITOEN + 1)
T
cy(CCLK)
8.11
ns
t
h(D)
data input hold time
[5]
0--ns
t
CSHOEH
CS HIGH to OE HIGH time 0.49 0 0.20 ns
t
OEHANV
OE HIGH to address invalid
time
0.20 0.20 2.44 ns
t
OELOEH
OE LOW to OE HIGH time 0.59 + (WAITRD
WAITOEN + 1) T
cy(CCLK)
0 + (WAITRD WAITOEN +
1) T
cy(CCLK)
0.10 + (WAITRD
WAITOEN + 1) T
cy(CCLK)
t
BLSLAV
BLS LOW to address valid
time
0.39 0 2.54 ns
t
CSHBLSH
CS HIGH to BLS HIGH time 0.88 0.49 0.68 ns
Write cycle parameters
[1][6]
t
CSLWEL
CS LOW to WE LOW time 0.88 + T
cy(CCLK)
(1 +
WAITWEN)
0.10 + T
cy(CCLK)
(1 +
WAITWEN)
0.20 + T
cy(CCLK)
(1 +
WAITWEN)
ns
t
CSLBLSL
CS LOW to BLS LOW time 0.88 0.49 0.98 ns
t
WELDV
WE LOW to data valid time 0.68 2.54 5.86 ns
t
CSLDV
CS LOW to data valid time 0 2.64 4.79 ns
t
WELWEH
WE LOW to WE HIGH time
[3]
0.78 + T
cy(CCLK)
(WAITWR WAITWEN + 1)
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 1)
0.10 + T
cy(CCLK)
(WAITWR WAITWEN + 1)
ns
t
BLSLBLSH
BLS LOW to BLS HIGH
time
[3]
0.88 + T
cy(CCLK)
(WAITWR WAITWEN + 3)
0 + T
cy(CCLK)
(WAITWR
WAITWEN + 3)
0.59 + T
cy(CCLK)
(WAITWR WAITWEN + 3)
ns
t
WEHANV
WE HIGH to address invalid
time
[3]
0 + T
cy(CCLK)
0.20 + T
cy(CCLK)
2.74 + T
cy(CCLK)
ns
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
LPC2420_60 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6.2 — 16 October 2013 60 of 87
NXP Semiconductors
LPC2420/2460
Flashless 16-bit/32-bit microcontroller
[1] V
OH
= 2.5 V, V
OL
= 0.2 V.
[2] V
IH
= 2.5 V, V
IL
= 0.5 V.
[3] T
cy(CCLK)
=
1
CCLK
.
[4] Latest of address valid, CS
LOW, OE LOW to data valid.
[5] Earliest of CS
HIGH, OE HIGH, address change to data invalid.
[6] Byte lane state bit (PB) = 1.
t
WEHDNV
WE HIGH to data invalid
time
[3]
0.78 + T
cy(CCLK)
2.54 + T
cy(CCLK)
5.96 + T
cy(CCLK)
ns
t
BLSHANV
BLS HIGH to address
invalid time
[3]
0.29 0.20 2.54 ns
t
BLSHDNV
BLS HIGH to data invalid
time
[3]
0 2.545.37ns
Table 14. Dynamic characteristics: Static external memory interface
…continued
C
L
=30pF, T
amb
=
40
C to 85
C, V
DD(DCDC)(3V3)
= V
DD(3V3)
= 3.0 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit

LPC2420FET208,551

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
ARM Microcontrollers - MCU 16b ROMLess 160I/O
Lifecycle:
New from this manufacturer.
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