16
LTC1735-1
APPLICATIO S I FOR ATIO
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U
When adjusting the gate drive level, the final arbiter is the
total input current for the regulator. If you make a change
and the input current decreases, then you improved the
efficiency. If there is no change in input current, then there
is no change in efficiency.
SENSE
+
/SENSE
Pins
The common mode input range of the current comparator
is from 0V to 1.1(INTV
CC
). Continuous linear operation is
guaranteed throughout this range allowing output volt-
ages anywhere from 0.8V to 7V. A differential NPN input
stage is used and is biased with internal resistors from an
internal 2.4V source as shown in the Functional Diagram.
This causes current either to be sourced or sunk by these
pins depending on the output voltage. If the output voltage
is below 2.4V, current will flow out of both SENSE pins to
the main output. This forces a minimum load current that
can be fulfilled by the V
OUT
resistive divider. The maxi-
mum current flowing out of the SENSE pins is:
I
SENSE
+
+ I
SENSE
= (2.4V – V
OUT
)/24k
Since V
OSENSE
is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 3 to have a maximum value to
absorb this current:
R Max k
V
VV
OUT
124
08
24
()
.
.–
=
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32k. Note that for output voltages above
2.4V no maximum value of R1 is necessary to absorb the
sense currents; however, R1 is still bounded by the
V
OSENSE
feedback current.
Soft-Start/Run Function
The RUN/SS pin is a multipurpose pin that provides a soft-
start function and a means to shut down the LTC1735-1.
Soft-start reduces surge currents from V
IN
by gradually
increasing the controller’s current limit I
TH(MAX)
. This pin
can also be used for power supply sequencing.
Pulling the RUN/SS pin below 1.5V puts the LTC1735-1
into a low quiescent current shutdown (I
Q
< 25µA). This
pin can be driven directly from logic as shown in Figures
4 and 5. Releasing the RUN/SS pin allows an internal
1.2µA current source to charge up the external soft-start
capacitor C
SS.
If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
T
V
A
CsFC
DELAY SS SS
=
µ
()
15
12
125
.
.
./
When the voltage on RUN/SS reaches 1.5V the
LTC1735-1 begins operating with a current limit at ap-
proximately 25mV/R
SENSE
. As the voltage on RUN/SS
increases from 1.5V to 3V, the internal current limit is
increased from 25mV/R
SENSE
to 75mV/R
SENSE
. The out-
put current limit ramps up slowly, taking an additional
1.25s/µF to reach full current. Ramping the output cur-
rent slowly reduces the starting surge current
required from the input supply.
Diode D1 in Figure 4 and Figure 5 reduces the start delay
while allowing C
SS
to charge up slowly for the soft-start
function. This diode and C
SS
can be deleted if soft-start is
not needed. The RUN/SS pin has an internal 6V zener
clamp (see Functional Diagram).
Figure 5. RUN/SS Pin Interfacing with Latchoff Defeated
Figure 4. RUN/SS Pin Interfacing
3.3V OR 5V RUN/SS RUN/SS
D1
C
SS
C
SS
1735-1 F04
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
D1
C
SS
R
SS
C
SS
R
SS
1735-1 F05
(a) (b)
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to shut off the
controller and latchoff when an overcurrent condition is
detected. The RUN/SS capacitor C
SS
is used initially to
turn on and limit the inrush current of the controller. After
the controller has been started and given adequate time to
charge up the output capacitor and provide full load
17
LTC1735-1
APPLICATIO S I FOR ATIO
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current, C
SS
is used as a short-circuit timer. If the output
voltage falls to less than 70% of its nominal output voltage
after
C
SS
reaches 4.1V, the assumption is made that the
output is in a severe overcurrent and/or short-circuit
condition and C
SS
begins discharging. If the condition
lasts for a long enough period as determined by the size of
C
SS
, the controller will be shut down until the RUN/SS pin
voltage is recycled.
This built-in latchoff can be overridden by providing a
current >5µA at a compliance of 5V to the RUN/SS pin as
shown in Figure 5a. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
conditions. When deriving the 5µA current from V
IN
as in
Figure 5a, current latchoff is always defeated. The diode
connecting this pull-up resistor to INTV
CC
, as in Figure 5b,
eliminates any extra supply current during shutdown
while eliminating the INTV
CC
loading from preventing
controller start-up. If the voltage on C
SS
does not exceed
4.1V, the overcurrent latch is not armed and the function
is disabled.
Why should you defeat current latchoff? During the
prototyping stage of a design, there may be a problem with
noise pickup or poor layout causing the protection circuit
to latch off. Defeating this feature will easily allow trouble-
shooting of the circuit and PC layout. The internal short
circuit and foldback current limiting still remains active,
thereby protecting the power supply system from failure.
After the design is complete, a decision can be made
whether to enable the latchoff feature.
The value of the soft-start capacitor C
SS
will need to be
scaled with output current, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
) (10
–4
) (R
SENSE
)
The minimum recommended soft-start capacitor of
C
SS
= 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC1735-1 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R
SENSE
.
The LTC1735-1 includes current foldback to help further
limit load current when the output is shorted to ground. If
the output falls by more than half, then the maximum
sense voltage is progressively lowered from 75mV to
30mV. Under short-circuit conditions with very low duty
cycles, the LTC1735-1 will begin cycle skipping in order to
limit the short-circuit current. In this situation the bottom
MOSFET will be conducting the peak current. The short-
circuit ripple current is determined by the minimum on-
time t
ON(MIN)
of the LTC1735-1 (less than 200ns), the
input voltage, and inductor value:
I
L(SC)
= t
ON(MIN)
(V
IN
/L)
The resulting short circuit-current is:
I
mV
R
I
SC
SENSE
LSC
=+
30 1
2
()
The current foldback function is always active and is not
effected by the current latchoff function.
Fault Conditions: Output Overvoltage Protection
(Crowbar)
The output overvoltage crowbar is designed to blow a
system fuse in the input lead when the output of the
regulator rises much higher than nominal levels. This
condition causes huge currents to flow, much greater than
in normal operation. This feature is designed to protect
against a shorted top MOSFET; it does not protect against
a failure of the controller itself.
The comparator (OV in the Functional Diagram) detects
overvoltage faults greater than 7.5% above the nominal
output voltage. When this condition is sensed the top
MOSFET is turned off and the bottom MOSFET is forced
on. The bottom MOSFET remains on continuously for as
long as the OV condition persists; if V
OUT
returns to a safe
level, normal operation automatically resumes. Note that
dynamically changing the output voltage may cause over-
voltage protection to be momentarily activated during
output voltage decreases. This will not cause permanent
latchoff nor will it disrupt the desired voltage change.
With soft-latch overvoltage protection, dynamically chang-
ing the output voltage is allowed and the overvoltage
protection tracks the newly programmed output voltage,
always protecting the load (CPU).
18
LTC1735-1
APPLICATIO S I FOR ATIO
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Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest amount of time
that the LTC1735-1 is capable of turning the top MOSFET
on and off again. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle applications may approach this minimum
on-time limit and care should be taken to ensure that:
t
V
Vf
ON MIN
OUT
IN
()
()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1735-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC1735-1 in a properly
configured application is less than 200ns. However, as the
peak sense voltage decreases, the minimum on-time
gradually increases as shown in Figure 6. This is of
particular concern in forced continuous applications with
low ripple current at light loads. If the duty cycle drops
below the minimum on-time limit in this situation, a
significant amount of cycle skipping can occur with corre-
spondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that is low enough
to provide sufficient ripple amplitude to meet the mini-
mum on-time requirement.
As a general rule keep the
inductor ripple current equal or greater than 30% of
I
OUT(MAX)
at V
IN(MAX)
.
PGOOD Pin Operation
The PGOOD pin is a multifunction pin intended primarily to
indicate when the output voltage is within ±7.5% of its
nominal set point. A window comparator monitors the
V
OSENSE
pin and activates an open-drain internal MOSFET
that pulls down the PGOOD pin when the output voltage is
out of regulation. Normally a 10k to 100k pull-up resistor
is connected to this pin from a voltage source such as
INT
VCC
. Do not apply a voltage greater than INTV
CC
to this
pin. Dynamically changing the output voltage between two
voltage levels greater that 7.5% apart from each other will
invoke the power good indication, causing the PGOOD
output to go low until the new output voltage is reached.
When the DC voltage on the PGOOD pin drops below its
0.8V threshold, continuous mode operation is forced. In
this case, the top and bottom MOSFETs continue to be
driven synchronously regardless of the load on the main
output. Burst Mode operation is disabled and current
reversal is allowed in the inductor. This mode is forced
whenever the output voltage is not within its 7.5%
window.
In addition to providing a power good output, the PGOOD
pin provides a logic input to force continuous synchro-
nous operation and allow synchronization to an external
clock.
The internal LTC1735-1 oscillator can be synchronized to
an external oscillator by applying a clock signal to the
PGOOD pin though a series resistor with a signal ampli-
tude above 1.5V
P-P
. When synchronized to an external
frequency, Burst Mode operation is disabled but cycle
skipping is allowed at low load currents since current
reversal is inhibited. The bottom gate will come on every
10 clock cycles to assure the bootstrap capacitor is kept
refreshed. The rising edge of an external clock applied to
the PGOOD pin starts a new cycle. If the output voltage is
not within the 7.5% window around its nominal set point,
the open-drain PGOOD output will pull low, disabling the
external synchronization.
The following table summarizes the possible states avail-
able on the PGOOD pin.
I
L
/I
OUT(MAX)
(%)
0
MINIMUM ON-TIME (ns)
100
150
40
1736-1 F06
50
0
10
20
30
250
200
Figure 6. Minimum On-Time vs I
L

LTC1735CS-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Hi Eff Sync Buck Sw Reg
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