Si590/591
4 Rev. 1.2
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol Test Condition Min Typ Max Units
LVPECL Output Option
1
V
O
mid-level V
DD
– 1.42 V
DD
– 1.25 V
V
OD
swing (diff) 1.1
1.9 V
PP
V
SE
swing (single-ended) 0.55
0.95 V
PP
LVDS Output Option
2
V
O
mid-level
1.125 1.20 1.275 V
V
OD
swing (diff)
0.5 0.7 0.9 V
PP
CML Output Option
2
V
O
2.5/3.3 V option mid-level V
DD
– 1.30
V
1.8 V option mid-level V
DD
– 0.36
V
OD
2.5/3.3 V option swing (diff) 1.10 1.50 1.90
V
PP
1.8 V option swing (diff) 0.35 0.425 0.50
CMOS Output Option
3
V
OH
0.8 x V
DD
V
DD
V
V
OL
——0.4
Rise/Fall time (20/80%)
t
R,
t
F
LVPECL/LVDS/CML 350 ps
CMOS with C
L
=15pF 2 ns
Symmetry (duty cycle) SYM LVPECL: V
DD
– 1.3 V (diff)
LVDS: 1.25 V (diff)
CMOS: V
DD
/2
45 55 %
Notes:
1. 50 to V
DD
– 2.0 V.
2. R
term
= 100 (differential).
3. C
L
= 15 pF. Sinking or sourcing 12 mA for V
DD
= 3.3V, 6mA for V
DD
= 2.5V, 3mA for V
DD
= 1.8 V.
Table 4. CLK± Output Phase Jitter
Parameter Symbol Test Condition Min Typ Max Units
Phase Jitter (RMS)
1
for 50 MHz < F
OUT
< 810 MHz
(LVPECL/LVDS/CML)
J
12 kHz to 20 MHz 0.5 1.0 ps
Phase Jitter (RMS)
1
(LVPECL/LVDS/CML)
J
12 kHz to 20 MHz,
155.52 MHz output frequency
—0.40.7ps
Phase Jitter (RMS)
2
for 50 MHz < F
OUT
< 160 MHz
(CMOS)
J
12 kHz to 20 MHz 0.6 1.0 ps
Notes:
1. Refer to AN256 for further information.
2. Single-ended CMOS output phase jitter measured using 33 series termination into 50 phase noise test equipment.
3.3 V supply voltage option only.
Si590/591
Rev. 1.2 5
\
Table 5. CLK± Output Period Jitter
Parameter Symbol Test Condition Min Typ Max Units
Period Jitter* J
PER
RMS 3 ps
Peak-to-Peak 35
*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.
Table 6. Environmental Compliance and Package Information
Parameter Conditions/Test Method
Mechanical Shock MIL-STD-883, Method 2002
Mechanical Vibration MIL-STD-883, Method 2007
Solderability MIL-STD-883, Method 2003
Gross and Fine Leak MIL-STD-883, Method 1014
Resistance to Solder Heat MIL-STD-883, Method 2036
Contact Pads Gold over Nickel
Table 7. Thermal Characteristics
(Typical values T
A
=2C, V
DD
=3.3V)
Parameter Symbol Test Condition Min Typ Max Unit
5x7mm, Thermal Resistance Junction to
Ambient
JA
Still Air 84.6 °C/W
5x7mm, Thermal Resistance Junction to
Case
JC
Still Air 38.8 °C/W
3.2x5mm, Thermal Resistance Junction to
Ambient
JA
Still Air 31.1 °C/W
3.2x5mm, Thermal Resistance Junction to
Case
JC
Still Air 13.3 °C/W
Ambient Temperature T
A
–40 85 °C
Junction Temperature T
J
——125°C
Si590/591
6 Rev. 1.2
Table 8. Absolute Maximum Ratings
1
Parameter
Symbol Rating Units
Maximum Operating Temperature T
AMAX
85 ºC
Supply Voltage, 1.8 V Option V
DD
–0.5 to +1.9 V
Supply Voltage, 2.5/3.3 V Option V
DD
–0.5 to +3.8 V
Input Voltage (any input pin) V
I
–0.5 to V
DD
+ 0.3 V
Storage Temperature T
S
–55 to +125 ºC
ESD Sensitivity (HBM, per JESD22-A114) ESD 2500 V
Soldering Temperature (Pb-free profile)
2
T
PEAK
260 ºC
Soldering Temperature Time @ T
PEAK
(Pb-free profile)
2
t
P
20–40 seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at
www.silabs.com/VCXO for further information, including soldering profiles.

591KA148M500DG

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Standard Clock Oscillators Differential/single-ended; single frequency XO; OE pin 1; 10-810 MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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