DS1844
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Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 4 details how
data transfer is accomplished on the two-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a 9
th
bit.
Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz clock rate)
are defined. The DS1844 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into account. A master must signal an end of data to the slave
by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the master to generate the STOP condition.
1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master
is the command/control byte. Next follows a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2. Data transfer from a slave transmitter to a master receiver. The 1
st
byte (the command/control
byte) is transmitted by the master. The slave then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to the master. The master returns an acknowledge
bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not
acknowledge’ can be returned.
The master device generates all serial clock pulses and the START and STOP conditions. A transfer is
ended with a STOP condition or with a repeated START condition. Since a repeated START condition is
also the beginning of the next serial transfer, the bus will not be released.
The DS1844 may operate in the following two modes:
1. Slave receiver mode: Serial data and clock are received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after reception of the slave (device) address and direction bit.
2. Slave transmitter mode: The 1
st
byte is received and handled as in the slave receiver mode.
However, in this mode the direction bit will indicate that the transfer direction is reversed. Serial
data is transmitted on SDA by the DS1844 while the serial clock is input on SCL. START and
STOP conditions are recognized as the beginning and end of a serial transfer.
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SLAVE ADDRESS
A command/control byte is the 1
st
byte received following the START condition from the master device.
The command/control byte consists of a 4-bit control code. For the DS1844, this is set as 0101 binary for
read/write operations. The next 3 bits of the command/ control byte are the device select bits or slave
address (A2, A1, A0). They are used by the master device to select which of eight devices is to be
accessed. When reading or writing the DS1844, the device-select bits must match the device-select pins
(A2, A1, A0). The last bit of the command/control byte (R/W) defines the operation to be performed.
When set to a 1 a read operation is selected, and when set to a 0 a write operation is selected. Figure 5
shows the command/control byte structure for the DS1844.
Following the START condition, the DS1844 monitors the SDA bus checking the device type identifier
being transmitted. Upon receiving the 0101 control code, the appropriate device address bits, and the
read/write bit, the slave device outputs an acknowledge signal on the SDA line.
COMMAND AND PROTOCOL
The command and protocol structure of the DS1844 allows the user to read or write the potentiometer(s).
Additionally, the 2-wire command/protocol structure of the DS1844 will support eight different devices
and a maximum of 32 channels that can be uniquely controlled. The command structures for the device
are presented in Figures 6 and 7. Potentiometer data values and control and command values are always
transmitted most significant bit (MSB) first. During communications, the receiving unit always generates
the acknowledgement.
Reading the DS1844
As shown in Figure 6, the DS1844 provides one read command operation. This operation allows the user
to read all potentiometers. Specifically, the R/W bit of the command/control byte is set equal to a 1 for a
read operation. Communication to read the DS1844 begins with a START condition which is issued by
the master device. The command/control byte from the master device will follow the START condition.
Once the command/control byte has been received by the DS1844, the part will respond with an
ACKNOWLEDGE. The read/write bit of the command/control byte, as stated, should be set equal to 1
for reading the DS1844.
When the master has received the ACKNOWLEDGE from the DS1844, the master can then begin to
receive potentiometer wiper data. The value of the potentiometer-0 wiper position will be the first
returned from the DS1844, followed by potentiometer-1 and so forth. Once the 8 bits of the
potentiometer-0 wiper position have been transmitted, the master will need to issue an
ACKNOWLEDGE, unless it is the only byte to be read, in which case the master issues a NOT
ACKNOWLEDGE. If desired the master may stop the communication transfer at this point by issuing the
STOP condition. However, if the value of the remaining potentiometers is needed, transfer can continue
by clocking the 8 bits of the potentiometer-1 value, followed by an ACKNOWLEDGE, and so forth.
Final communication transfer is terminated by issuing the STOP command. Again, the flow of the read
operation is presented in Figure 6.
Writing the DS1844
A data flow diagram for writing the DS1844 is shown in Figure 7. The DS1844 has one write command
that is used to change the position(s) of the wiper. The 2-wire serial interface write structure is similar to
that of the 5-wire serial write. However, there are differences.
All the write operations begin with a START condition. Following the START condition, the master
device will issue the command/control byte. The read/write bit of the command/control byte will be set to
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0 for writing the DS1844. Once the command/control byte has been issued and the master receives the
acknowledgment from the DS1844, potentiometer wiper data is transmitted to the DS1844 by the master
device.
As in the case of the 5-wire serial protocol, a data byte for the DS1844 will contain potentiometer select
data and wiper position value. The six least significant bits of data specify the wiper position value while
the two most significant bits specify the potentiometer to be loaded. When the DS1844 has received the
data byte, it will respond with an ACKNOWLEDGE. At this point, the new wiper value for the
potentiometer selected will be updated in the DS1844. The master device, after the receipt of the
ACKNOWLEDGE, can continue to transmit additional data bytes or if the transaction is complete
respond with the STOP condition. Additionally, the DS1844 does not require a specific order for writing
a particular potentiometer wiper's data. The 2-wire serial timing diagram is presented in Figure 8.

DS1844S-050

Mfr. #:
Manufacturer:
Description:
IC POT DIG QUAD 50K 20-SOIC
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New from this manufacturer.
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