REV. B
AD807
–8–
AD807
COMPARATOR
STAGES AND
CLOCK RECOVERY
PLL
PIN
NIN
THRESHOLD
BIAS
⌺
+
+
IHYS
ITHR
SDOUT
POSITIVE
PEAK
DETECTOR
NEGATIVE
PEAK
DETECTOR
LEVEL-
SHIFT
UP
LEVEL-
SHIFT
DOWN
Figure 8. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
The phase-locked loop recovers clock and retimes data from
NRZ data. The architecture uses a frequency detector to aid
initial frequency acquisition; refer to Figure 9 for a block diagram.
Note the frequency detector is always in the circuit. When the
PLL is locked, the frequency error is zero and the frequency
detector has no further effect. Since the frequency detector is
always in the circuit, no control functions are needed to initiate
acquisition or change mode after acquisition.
⌺
⌽
DET
F
DET
DATA
INPUT
S + 1
RETIMING
DEVICE
1
S
VCO
RECOVERED CLOCK
OUTPUT
RETIMED DATA
OUTPUT
Figure 9. PLL Block Diagram
The frequency detector delivers pulses of current to the charge
pump to either raise or lower the frequency of the VCO. During
the frequency acquisition process the frequency detector output
is a series of pulses of width equal to the period of the VCO.
These pulses occur on the cycle slips between the data frequency
and the VCO frequency. With a maximum density data pattern
(1010 . . . ), every cycle slip will produce a pulse at the frequency
detector output. However, with random data, not every cycle
slip produces a pulse. The density of pulses at the frequency
detector output increases with the density of data transitions. The
probability that a cycle slip will produce a pulse increases as the
frequency error approaches zero. After the frequency error has
been reduced to zero, the frequency detector output will have
no further pulses. At this point the PLL begins the process of phase
acquisition, with a settling time of roughly 2000 bit periods.
Jitter caused by variations of density of data transitions (pattern
jitter) is virtually eliminated by use of a new phase detector
(patented). Briefly, the measurement of zero phase error does
not cause the VCO phase to increase to above the average run
rate set by the data frequency. The jitter created by a 2
7
–1
pseudorandom code is 1/2 degree, and this is small compared to
random jitter.
The jitter bandwidth for the PLL is 0.06% of the center fre-
quency. This figure is chosen so that sinusoidal input jitter at
92 kHz will be attenuated by 3 dB.
The damping ratio of the PLL is user programmable with a
single external capacitor. At 155 MHz, a damping ratio of 5
is obtained with a 0.15 µF capacitor. More generally, the damp-
ing ratio scales as (f
DATA
× C
D
)
1/2
.
A lower damping ratio allows a faster frequency acquisition;
generally the acquisition time scales directly with the capacitor
value. However, at damping ratios approaching one, the acquisi-
tion time no longer scales directly with capacitor value. The
acquisition time has two components: frequency acquisition and
phase acquisition. The frequency acquisition always scales with
capacitance, but the phase acquisition is set by the loop band-
width of the PLL and is independent of the damping ratio.
Thus, the 0.06% fractional loop bandwidth sets a minimum
acquisition time of 2000 bit periods. Note the acquisition time
for a damping factor of one is 15,000 bit periods. This comprises
13,000 bit periods for frequency acquisition and 2,000 bit peri-
ods for phase acquisition. Compare this to the 400,000 bit
periods acquisition time specified for a damping ratio of 5; this
consists entirely of frequency acquisition, and the 2,000 bit
periods of phase acquisition is negligible.
While a lower damping ratio affords faster acquisition, it also
allows more peaking in the jitter transfer response (jitter peaking).
For example, with a damping ratio of 10, the jitter peaking is
0.02 dB, but with a damping ratio of 1, the peaking is 2 dB.
Center Frequency Clamp (Figure 10)
An N-channel FET circuit can be used to bring the AD807 VCO
center frequency to within ±10% of 155 MHz when SDOUT
indicates a Loss of Signal (LOS). This effectively reduces the
frequency acquisition time by reducing the frequency error
between the VCO frequency and the input data frequency at
clamp release. The N-FET can have “on” resistance as high as
1 kΩ and still attain effective clamping. However, the chosen
N-FET should have greater than 10 MΩ “off” resistance and
less than 100 nA leakage current (source and drain) so as not to
alter normal PLL performance.
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
AD807
DATAOUTN
DATAOUTP
V
CC2
CLKOUTN
CLKOUTP
V
CC1
CF1
CF2
V
EE
SDOUT
AV
CC2
PIN
NIN
AV
CC1
THRADJ
AV
EE
N_FET
C
D
Figure 10. Center Frequency Clamp Schematic
FREQUENCY – Hz
10 20k
0.02dB/DIV
100 1k 10k
C
D
PEAK
0.1
0.15
0.22
0.33
0.12
0.08
0.06
0.04
Figure 11. Jitter Transfer vs. C
D
