Technical Note
13/18
BU6520KV,BU6521KV
www.rohm.com
2010.02 - Rev.C
© 2010 ROHM Co., Ltd. All rights reserved.
2. The 2 line formula serial interface format
Slave address is 70h.
The sub-address is incremented automatically when accessing it (read / write) continuously 2 times or more.
S = START condition A(S) = Acknowledge by slave NA(S) = Not acknowledge by slave
P = STOP condition A(M) = Acknowledge by master NA(M) = Not acknowledge by master
Write sequence
S
Slave address
(70h)
W
(0)
A(S) Sub address A(S) Data A(S) Data A(S) Data
A(S)/
NA(S)
P
Read sequence
S
Slave address
(70h)
W
(0)
A(S) Sub address S
Slave address
(70h)
A(M)/
NA(M)
PA(S)
R
(1)
A(S) Data A(M) Data
Fig.12 2-line serial interface format
3. SPI-bus format
Fig.13 SPI-bus interface wave form
* REG_WPB, REG_SCEB, SWDATA, and SRDATA in figure are the register names, and the each function is as follows.
REG_WPB ：Set WP Terminal logic. Register value is output directly.
REG_SCEB ：Set SCEB Terminal logic. Register value is output directly.
SWDATA[7:0]：Write data to EEPROM. Transfers MSB the first.
SRDATA[7:0] ：Read data from EEPROM. Converts MSB the first.
The SCK clock frequency is as follows.
SCK frequency = CAMCKI frequency ÷ 2
(SPIPREDIV+1)
÷ (SPIDIV+1)
Register range : SPIPREDIV = 0 to 7, SPIDIV = 0 to 31
When CAMCKI is 27MHz, SCK becomes 3.3 kHz from 13.5 MHz.
WPB
H'/'L' level is set by the REG_WPB register.
SCEB
H'/'L' level is set by the REG_SCEB register.
SCK
SDO W7W6W5W4W3W2W1W0
SDI R7R6R5R4R3R2R1R0
The data written in
the SWDATA register is set.
It is possible to read it
from the SRDATA register.
Fig.10
SDI
SCLK
データ送受信波形
1-7 8S
1-7 8 9
STOP
condition
9 1-7 8
9 P
ACK
ACKSub address Data ACK
Slave
address
R/W
START
condition
Fig.11 Waveform of date transmission part
SDA
SDC
