0.01 0.1 1 10 100 1000 10000 100000
0
50
100
150
20
40
60
80
100
120
140
f (KHz)
G [dB]
Phase
Figure 20. E/A frequency response.
-50 -25 0 25 50 75 100 125 150
28
30
32
34
36
38
40
42
T
j
(
°C
)
Dela
y
to output (ns)
PIN10 = OPEN
1V pulse
on PIN13
Figure 19. Delay to output vs junction temperature.
-50 -25 0 25 50 75 100 125 150
280
290
300
310
320
Tj (°C)
fsw (KHz)
Rt= 4.5Kohm, Ct = 1nF
Vcc = 15V, V15= 0
Figure 16. Switching frequency vs. temperature.
246810
300
600
900
1,200
1,500
Timing capacitor Ct [nF]
Dead time [ns]
Rt =4.5Kohm
V15 = 0V
V15 = Vref
Figure 17. Dead time vs Ct.
0 102030405060708090100
1
1.5
2
2.5
3
3.5
Duty Cycle [%]
DC Control Voltage Vpin3 [V]
Rt = 4.5Kohm,
Ct = 1nF
V15 = 0V
V15 = Vref
Figure 18. Maximum Duty Cycle vs Vpin3.
-50 -25 0 25 50 75 100 125 150
280
290
300
310
320
TjC)
fsw (KHz)
Rt= 4.5Kohm, Ct = 1nF
Vcc = 15V, V15=Vref
Figure 15. Switching frequency vs. tempera-
ture.
L5991 - L5991A
7/23
STANDBY FUNCTION
The standby function, optimized for flyback topol-
ogy, automatically detects a light load condition
for the converter and decreases the oscillator fre-
quency on that occurrence. The normal oscillation
frequency is automatically resumed when the out-
put load builds up and exceeds a defined thresh-
old.
This function allows to minimize power losses re-
lated to switching frequency, which represent the
majority of losses in a lightly loaded flyback, with-
out giving up the advantages of a higher switching
frequency at heavy load.
This is accomplished by monitoring the output of
the Error Amplifier (V
COMP
) that depends linearly
on the peak primary current, except for an offset.
If the the peak primary current decreases (as a re-
sult of a decrease of the power demanded by the
load) and V
COMP
falls below a fixed threshold
(V
T1
), the oscillator frequency will be set to a
lower value (f
SB
). When the peak primary current
increases and V
COMP
exceeds a second threshold
(V
T2
) the oscillator frequency is set to the normal
value (f
osc
). An appropriate hysteresis (V
T2
-V
T1
)
prevents undesired frequency change when
power is such that V
COMP
moves close to the
threshold. This operation is shown in fig. 21.
Both the normal and the standby frequency are
externally programmable. V
T1
and V
T2
are inter-
nally fixed but it is possible to adjust the thresh-
olds in terms of input power level.
APPLICATION INFORMATION
Detailed Pin Function Description
Pin 1.
SYNC (In/Out Synchronization). This func-
tion allows the IC’s oscillator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 23 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600
µ
A internal sink current gener-
ator. During the falling edge, that is when the
pulse is released, the 600
µ
A pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 22, some practical examples of synchroniz-
ing the L5991 are given.
Since the device automatically diminishes its op-
erating frequency under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operation and not to standby.
Pin 2.
RCT (Oscillator). Two resistors (R
A
and R
B
)
and one capacitor (C
T
), connected as shown in
fig. 23, allow to set separately the operating fre-
quency of the oscillator in normal operation (f
osc
)
and in standby mode (f
SB
).
C
T
is charged from Vref through R
A
and R
B
in nor-
mal operation (STANDBY = HIGH), through R
A
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is gen-
erated.
When the voltage on C
T
reaches 3V, the capaci-
tor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
1234
VCOMP
Pin
f
osc
f
SB
Stand-by
Normal operation
V
T
1
P
NO
P
SB
V
T
2
Figure 21. Standby dynamic operation.
L5991 L5991
R
A
VREF
SYNCSYNC
RCTRCT
L4981A
(MASTER)
L5991
(SLAVE)
R
A
VREFSYNC
RCT
R
OSC
C
OSC
C
T
L5991
(MASTER)
L4981A
(SLAVE)
SYNC
R
OSC
C
T
C
OSC
SYNC
(a) (b) (c)
R
A
D97IN728A
C
T
VREF
4
1
2
1
2
16
1817
4
2
1
RCT
12
4
16
17 18
ST-BY
16
R
B
ST-BY
16
R
B
R
B
16
ST-BY
Figure 22. Synchronizing the L5991.
L5991 - L5991A
8/23
The oscillation frequency can be established with
the aid of the diagrams of fig. 14, where R
T
will be
intended as the parallel of R
A
and R
B
in normal
operation and R
T
= R
A
in standby, or considering
the following approximate relationships:
f
osc
1
C
T
(
0.693
(
R
A
// R
B
)
+
K
T
(
1
)
,
which gives the normal operating frequency, and:
f
SB
1
C
T
(
0.693
R
A
+
K
T
)
(
2
)
,
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
R
A
//
R
B
=
R
A
R
B
R
A
+
R
B
,
while K
T
is defined as:
K
T
=
90 V
15
=
VREF
160
V
15
=
GND
/OPEN
(
3
)
,
and is related to the duration of the falling-edge of
the sawtooth:
T
d
30
10
9
+
K
T
C
T
(
4
)
.
T
d
is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extreme of the
duty cycle range, D
x
(see pin 15 for D
X
definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
from fig. 14 or resulting from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from f
osc
to f
SB
, the ratio f
osc
/ f
SB
must not exceed 5.5.
If during normal operation the IC is to be synchro-
nized to an external oscillator, R
A
, R
B
and C
T
should be selected for a f
osc
lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
Pin 3.
DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme D
x
(see pin 15).
If D
max
is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V
3
= 5 - 2
(2-Dmax)
(5)
D
max
is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 24),
thus in case the device is synchronized to an ex-
ternal frequency f
ext
(and therefore the oscillator
amplitude is reduced), (5) changes into:
V
3
=
5
4
exp
D
max
R
T
C
T
f
ext
(6)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. D
MAX
= D
X
), the pin has to be left float-
ing. An internal pull-up (see fig. 24) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
+
-
R2R3
R1
CLAMP
D1
50
R
A
C
T
D
R
Q
600µA
D97IN729A
V
REF
RCT
SYNC
CLK
2
4
1
16ST-BY
R
B
STANDBY
Figure 23. Oscillator and synchronization internal schematic.
L5991 - L5991A
9/23

E-L5991AD

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Switching Controllers Prog Current Mode
Lifecycle:
New from this manufacturer.
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