during ESD tests), it can be connected to VREF
through a 4.7k
Ω
resistor.
Pin 4.
VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V
±
1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1
µ
F typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affecting the reference.
Before device turn-on, this pin has a sink current ca-
pability of 0.5mA.
Pin 5.
VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
Pin 6.
COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple of compensation techniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into ac-
count. In particular, this means that the open-loop
crossover frequency must not exceed f
SB
/4
÷
f
SB
/5.
The voltage on pin 6 is monitored in order to re-
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7.
SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-start time, is approximately:
T
ss
≅
3
⋅
R
sense
⋅
I
Qpk
I
SSC
⋅
C
ss
(7)
where R
sense
is the current sense resistor (see pin
13) and I
Qpk
is the switch peak current (flowing
through R
sense
), which depends on the output
load. Usually, C
SS
is selected for a T
SS
in the or-
der of milliseconds.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 25, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 26 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as ’hiccup" period, is approximately given by:
T
hic
≅
4.5
⋅
1
I
SSC
+
1
I
SSD
⋅
C
ss
(
8
)
+
-
R2
R1
R
A
C
T
D97IN727A
V
REF
RCT
DC
TO PWM LOGIC
4
3
2
23K
28K
3µA
R
B
ST-BY
16
Figure 24. Duty cycle control.
V
OUT
T
ON
D.C.M. C.C.M.
D
A
B
C
I
Qpk
T
ON(min)
1-2 ·I
Qpk
I
Qpk(max)
I
OUT
I
SHORT
I
OUT(max)
D97IN495
Figure 25. Regulation characteristic and re-
lated quantities.
L5991 - L5991A
10/23
