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ADG451BRUZ-REEL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
ADG451/ADG452/ADG453
Rev. C | Page 10 of 16
05239-009
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE (V)
15–15 –12 –9 –6 –3 0 3 6 9 12
LEAKAGE CURRENT (nA)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
I
D
(ON)
I
D
(OFF)
I
S
(OFF)
V
DD
= +15V
V
SS
= –15V
T
A
=+25°C
V
L
=+5V
Figure 11. Leakage Currents as a Function of V
D
(V
S
)
05239-010
FREQUENCY (MHz)
100110
OFF ISOLATION (dB)
70
60
50
40
30
0
20
10
V
DD
= +15V
V
SS
=–15V
V
L
=+5V
Figure 12. Off Isolation vs. Frequency
05239-011
FREQUENCY (Hz)
100M100 1k 10k 100k 10M1M
CROSSTALK (dB)
120
100
80
60
40
20
0
V
DD
= +15V
V
SS
=–15V
V
L
=+5V
R
LOAD
=50Ω
Figure 13. Crosstalk vs. Frequency
05239-012
FREQUENCY (MHz)
2001 10 100
LOSS (dB)
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
V
DD
= +15V
V
SS
= –15V
V
L
=+5V
Figure 14. Frequency Response with Switch On
ADG451/ADG452/ADG453
Rev. C | Page 11 of 16
TERMINOLOGY
R
ON
Ohmic resistance between D and S.
ΔR
ON
On resistance match between any two channels, that is, R
ON
maximum minus R
ON
minimum.
R
FLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
I
S
(OFF)
Source leakage current with the switch off.
I
D
(OFF)
Drain leakage current with the switch off.
I
D
, I
S
(ON)
Channel leakage current with the switch on.
V
D
(V
S
)
Analog voltage on Terminal D and Terminal S.
C
S
(OFF)
Off switch source capacitance.
C
D
(OFF)
Off switch drain capacitance.
C
D
(ON), C
S
(ON)
On switch capacitance.
t
ON
Delay between applying the digital control input and the output
switching on. See
Figure 19.
t
OFF
Delay between applying the digital control input and the output
switching off.
t
D
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another. See
Figure 20.
Crosstalk
A measure of unwanted signal coupled through from one
channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ADG451/ADG452/ADG453
Rev. C | Page 12 of 16
APPLICATIONS
Figure 15 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer, and the output operational
amplifier is an
AD711. During track mode, SW1 is closed, and
the output, V
OUT
, follows the input signal, V
IN
. In hold mode,
SW1 is opened, and the signal is held by the hold capacitor, C
H
.
SD
V
OUT
SD
–15V
+15V +5V
C
C
1000pF
2200pF
R
C
75Ω
1213
45
SW1
ADG451/
ADG452/
ADG453
–15V
+15V
V
IN
AD845
–15V
+15V
AD711
SW2
CH
2200pF
05239-013
Figure 15. Fast, Accurate Sample-and-Hold Circuit
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG451/ADG452/ADG453
minimize this droop due to their low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Because both
switches are at the same potential, they have a differential effect
on the op amp,
AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network, R
C
and C
C
. This compensation network reduces the
hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ADG451BRUZ-REEL7

Mfr. #:
Buy ADG451BRUZ-REEL7
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs LC2MOS 5 Ohm SPST
Lifecycle:
New from this manufacturer.
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