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LT1236BILS8-5#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LT1236LS8
7
1236ls8f
applicaTions inForMaTion
Effect of Reference Drift on System Accuracy
A large portion of the temperature drift error budget in
many systems is the system reference voltage. This graph
indicates the maximum temperature coefficient allowable
if the reference is to contribute no more than 0.5LSB error
to the overall system performance. The example shown is
a 12-bit system designed to operate over a temperature
range from 25°C to 65°C. Assuming the system calibration
is performed at 25°C, the temperature span is 40°C. It can
be seen from the graph that the temperature coefficient
of the reference must be no worse than 3ppm/°C if it is
to contribute less than 0.5LSB error. For this reason, the
LT1236LS8 has been optimized for low drift.
Trimming Output Voltage
The LT1236LS8 has an output voltage trim pin, but the
temperature drift of the nominal 4V open circuit voltage
at pin 5 is about –1.7mV/°C. For the voltage trimming not
to affect reference output temperature drift, the external
trim voltage must track the voltage on the trim pin. Input
impedance of the trim pin is about 100kΩ and attenua-
tion to the output is 13:1. The technique shown below
is suggested for trimming the output of the LT1236LS8
while maintaining minimum shift in output temperature
coefficient. The R1/R2 ratio is chosen to minimize interac-
tion of trimming and temperature drift shifts, so the exact
values shown should be used.
Capacitive Loading and Transient Response
The LT1236LS8 is stable with all capacitive loads, but for
optimum settling with load transients, output capacitance
should be under 1000pF. The output stage of the reference
is class AB with a fairly low idling current. This makes
transient response worst-case at light load currents.
Because of internal current drain on the output, actual
worst-case occurs at I
LOAD
= 0. Significantly better load
transient response is obtained by moving slightly away
from these points. See Load Transient Response curves
for details. In general, best transient response is obtained
when the output is sourcing current. In critical applica-
tions, a 10µF solid tantalum capacitor with several ohms
in series provides optimum output bypass.
Load Regulation
The LT1236LS8 is capable of driving 10mA to a load. The
load regulation at the output of the LT1236LS8 is very
good, with a change of less than 25ppm/mA when driving
the load. However, the load current will cause a voltage
drop in the connecting wire between the LT1236LS8 and
the load. This IR drop is dependent on the resistance of
the connecting wire and will appear as additional load
regulation error. For example, 12 feet of #22 gauge wire or
1 foot of 0.025 inch printed circuit board trace will create
2mV loss at 10mA output current. This is equivalent to
1LSB in a 10V, 12-bit system.
There are three approaches that will reduce this effect. First,
limiting the distance between the LT1236LS8 and the load
will reduce the trace length, and improve load regulation.
Second, use wider traces for the connections between
the LT1236LS8 and the load to reduce IR drop. Finally,
TEMPERATURE SPAN (°C)
10
MAXIMUM TEMPERATURE COEFFICIENT FOR
0.5LSB ERROR (ppm/°C)
30
100
1236ls8 AI01
1.0
10
20 100
90
807060
50
40
8-BIT
10-BIT
12-BIT
14-BIT
LT1236LS8
OUT
IN
GND
TRIM
R1
27k
R2
50k
1N4148
V
OUT
1236ls8 AI02
Maximum Allowable Reference Drift
LT1236LS8
8
1236ls8f
applicaTions inForMaTion
LT1236LS8
OUT
GND
IN
LOAD
R1
220Ω
2N3906
R2*
INPUT
GROUND
RETURN
*OPTIONAL—REDUCES CURRENT IN OUTPUT SENSE
LEAD: R2 = 2.4k
1236ls8 AI04
LT1236LS8
OUT
IN
GND
KEEP THIS LINE RESISTANCE LOW
LOAD
+
INPUT
GROUND
RETURN
1236ls8 AI03
use a star-ground method, with the LT1236LS8 ground
tied directly to the load, rather than through a ground
plane or other shared ground trace. This last method will
reduce drop in the ground trace between the LT1236LS8
and the load. The ground wire in this case will carry only
approximately 1mA, which is the ground current of the
LT1236LS8, while the load return current will shunt to the
system ground separate from the reference-to-load path.
The following circuits show proper hook-up to minimize
errors due to ground loops and line losses. Losses in the
output lead can be greatly reduced by adding a PNP boost
transistor if load currents are 5mA or higher. R2 can be
added to further reduce current in the output sense lead.
Effects of Air Movement on Low Frequency Noise
The LT1236LS8 has very low noise because of the buried
zener used in its design. In the 0.1Hz to 10Hz band, peak-
to-peak noise is about 0.5ppm of the DC output. To achieve
this low noise, however, care must be taken to shield the
reference from ambient air turbulence. Air movement can
create noise because of thermoelectric differences between
IC package leads and printed circuit board materials and/or
sockets. Power dissipation in the reference, even though it
rarely exceeds 20mW, is enough to cause small tempera-
ture gradients in the package leads. Variations in thermal
resistance, caused by uneven air flow, create differential
lead temperatures, thereby causing thermoelectric voltage
noise at the output of the reference.
Series Mode with Boost Transistor
Standard Series Mode
Long-Term Drift
Long-term drift cannot be extrapolated from accelerated
high temperature testing. This erroneous technique gives
drift numbers that are wildly optimistic. The only way
long-term drift can be determined is to measure it over
the time interval of interest.
The LT1236LS8 long-term drift data was collected on 80
parts that were soldered into printed circuit boards similar
to a real world application. The boards were then placed
into a constant temperature oven with a T
A
= 35°C, their
outputs were scanned regularly and measured with an 8.5
digit DVM. Typical long-term drift is illustrated in Figure 1.
Figure 1. Long-Term Drift
HOURS
0
PPM
40
0
80
200
1236ls8 F01
–40
–80
–200
–160
160
–120
120
500 1000
1500 2000
NORMALIZED TO 10 HOURS
DUE TO SYSTEM WARM-UP
LT1236LS8
9
1236ls8f
applicaTions inForMaTion
Figure 2b. Hysteresis Plot –40°C to 85°C
Figure 2a. Hysteresis Plot 0°C to 70°C
DISTRIBUTION (ppm)
–120
0
NUMBER OF UNITS
5
15
25
–80 –40 40 80 1200
35
10
20
30
1236ls8 F02b
25°C TO –40°C TO 25°C
25°C TO 85°C TO 25°C
DISTRIBUTION (ppm)
NUMBER OF UNITS
20
18
50
16
14
12
10
–50 –10 90–30 10 7030
2
4
6
8
0
22
1236ls8 F02a
25°C TO 0°C TO 25°C
25°C TO 70°C TO 25°C
Hysteresis
Thermal hysteresis is a measure of change of output volt-
age as a result of temperature cycling. Figure 2a and 2b
illustrate the typical hysteresis based on data taken from
the LT1236LS8. A proprietary design technique minimizes
thermal hysteresis.
IR Reflow Shift
The mechanical stress of soldering a part to a board can
cause the output voltage to shift. Moreover, the heat of
an IR reflow or convection soldering oven can also cause
the output voltage to shift. The materials that make up a
semiconductor device and its package have different rates
of expansion and contraction. After a part undergoes the
extreme heat of a lead-free IR reflow profile, like the one
shown in Figure 3, the output voltage shifts. After the
device expands, due to the heat, and then contracts, the
Humidity Sensitivity
Plastic mold compounds absorb moisture. With changes
in relative humidity, plastic packaging materials change
the amount of pressure they apply to the die inside, which
can cause slight changes in the output of a voltage refer-
ence, usually on the order of 100ppm. The LS8 package is
hermetic, so it is not affected by humidity, and is therefore
more stable in environments where humidity may be a
concern. However, PC Board material may absorb moisture
and apply mechanical stress to the LT1236LS8. Proper
board materials and layout are essential.
Figure 3. Lead-Free Reflow Profile
Figure 4. Output Voltage Shift Due to IR Reflow
MINUTES
0
TEMPERATURE (°C)
150
225
8
1236ls8 F03
75
0
2
4
6
10
300
T = 150°C
T
S
= 190°C
T
L
= 217°C
T
P
= 260°C
380s
t
P
30s
t
L
130s
40s
120s
RAMP
DOWN
T
S(MAX)
= 200°C
RAMP TO
150°C
REFLOW SHIFT (%)
–0.05
0
NUMBER OF UNITS
2
4
6
–0.03 –0.01–0.04 –0.02 0.010
10
9
8
1
3
5
7
1236ls8 F04
1× REFLOW
3× REFLOW
24Hr REST
stresses on the die have changed position. This shift is
similar, but more extreme than thermal hysteresis.
Experimental results of IR reflow shift are shown below
in Figure 4. These results show only shift due to reflow
and not mechanical stress.
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LT1236BILS8-5#PBF

Mfr. #:
Buy LT1236BILS8-5#PBF
Manufacturer:
Analog Devices Inc.
Description:
Voltage References 5V Buried Zener 10ppm/C Reference, Hermetic Package
Lifecycle:
New from this manufacturer.
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