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LTC1647-3IGN#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
LTC1647-1/
LTC1647-2/LTC1647-3
10
1647fa
BLOCK DIAGRAMS
14
–
+
50μs
FILTER
–
+
1.21V
50mV
CHANNEL ONE
CHANNEL TWO
(DUPLICATE OF CHANNEL ONE)
10μA
CP
+
–
50μA
FAULT
2.45V
UVL
CHARGE
PUMP
REFERENCE 1.21V
SENSE2
4ON2
5FAULT2
1647-1/2/3 BD3
16V
CC2
12 GATE2
8GND
CP
V
CC
SELECTION
15SENSE1
13 GATE1
3FAULT1
2ON1
1V
CC1
LTC1647-3
V
CC
Selection Circuit
The LTC1647-3 features separate supply inputs (V
CC1
and V
CC2
) for each channel. The reference and charge
pump circuit draw supply current from the higher of the
two supplies. An internal V
CC
selection circuit detects and
makes the power connection automatically. This allows
a 3V channel to have standard MOSFET gate overdrive
when the other channel is 5V. An internal Zener clamps
GATE about 15V above V
CC
.
If both supplies are connected together (internally for
LTC1647-1 and LTC1647-2 or externally for LTC1647-3),
the reference and charge pump circuit draw equal current
from both pins.
APPLICATIONS INFORMATION
Electronic Circuit Breaker
Each channel of the LTC1647 features an electronic circuit
breaker to protect against excessive load current and short-
circuits. Load current is monitored by sense resistor R1 as
shown in Figure 1. The circuit breaker threshold, V
CB
, is
50mV and it exhibits a response time, t
FAULT
, of approximately
300ns. If the voltage between V
CC
and SENSE exceeds V
CB
for more than t
FAULT
, the circuit breaker trips and immediately
pulls GATE low with a 50mA current sink. The MOSFET turns
off and FAULT pulls low. The circuit breaker is cleared by
pulling the ON pin low for a period of at least t
RESET
(50μs).
A timing diagram of these events is shown in Figure 2.
The value of the sense resistor R1 is given by:
R1 = V
CB
/I
TRIP
(Ω)
LTC1647-1/
LTC1647-2/LTC1647-3
11
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APPLICATIONS INFORMATION
SENSE
15 13
ON1
2
FAULT
ON
V
CC
V
OUT
FAULT
3
GND
8
GATE
LTC1647-3
C1
10nF
1647-1/2/3 F01
R2
10Ω
*D1
DDZ23
R1
0.01Ω
Q1
IRF7413
C
LOAD
+
V
CC
1
R3
10k
*D1 REQUIRED FOR V
CC
> 10V
Figure 1. Supply Control Circuitry
t
FAULT
t
RESET
V
ON
V
CC
–
V
SENSE
V
GATE
V
FAULT
1647-1/2/3 F02
SENSE
V
CC
V
OUT
GATE
LTC1647
C1
10nF
C3
10nF
1647-1/2/3 F03
R2
10Ω
R1
0.01Ω
Q1
IRF7413
C
LOAD
I
PK
= 7.5A
I
AV
= 2.5A
I
TRIP
= V
CB
/R1 = 5A
t
DELAY
= 10μs
+
V
CC
R3
1.5k
Figure 2. Current Fault Timing
Figure 3. Filtering Current Ripple/Glitches
where V
CB
is the circuit breaker trip voltage (50mV) and
I
TRIP
is the value of the load current at which the circuit
breaker trips. Kelvin-sense layout techniques between
the sense resistor and the V
CC
and SENSE pins are highly
recommended for proper operation.
The circuit breaker trip voltage has a tolerance of 20%;
combined with a 5% sense resistor, the total tolerance is
25%. Therefore, calculate R1 based on a trip current I
TRIP
of no less than 125% of the maximum operating current.
Do not neglect the effect of ripple current, which adds to
the maximum DC component of the load current. Ripple
current may arise from any of several sources, but the
worst offenders are switching supplies.
A switching regulator on the load side will attempt to draw
some ripple current from the backplane and this current
passes through the sense resistor. Similarly, output ripple
from a switching regulator supplying the backplane will flow
through the sense resistor and into the load capacitor.
Minimize the effects of ripple current by either filtering the
V
OUT
line or adding an RC filter to the SENSE pin. A series
inductance of 1μH to 10μH inserted between Q1 and C
LOAD
is adequate ripple current suppression in most cases.
Alternatively, a filter, consisting of R3 and C3 (Figure 3),
simply filters the ripple component from the SENSE pin at the
expense of response time. The added delay is given by:
t
DELAY
= –R3•C3•ln[1 – (V
CB
/R1 – I
AV
)/(I
PK
– I
AV
)]
Power MOSFET Selection
Power MOSFETs are classified into two catagories: standard
MOSFETs (R
DS(ON)
specified at V
GS
= 10V) and logic-level
MOSFETs (R
DS(ON)
specified at V
GS
= 5V). The absolute
maximum rating for V
GS
is typically 20V for standard
MOSFETs. The maximum rating for logic-level MOSFETs
is lower and ranges from 8V to 16V depending on the
manufacturer and specific part number. Some logic-level
MOSFETs have a 20V maximum V
GS
rating. The LTC1647
is primarily targeted for standard MOSFETs; low supply
voltage applications should use logic-level MOSFETs. GATE
overdrive as a function of V
CC
is illustrated in the Typical
Performance Curves. If lower GATE overdrive is desired,
connect a diode in series with a Zener between GATE and
V
CC
or between GATE and V
OUT
as shown in Figure 4. For
V
CC
V
OUT
*D1, D4 USER SELECTED VOLTAGE CLAMP
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
**D5 DDZ23 (23V) REQUIRED FOR V
CC
> 10V
1647-1/2/3 F04
R1
D1*
D2
1N4148 D4*
D2
1N4148
Q1
**D5
Figure 4. Optional Gate Clamp
LTC1647-1/
LTC1647-2/LTC1647-3
12
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APPLICATIONS INFORMATION
V
CC
+ Δ
V
GATE
V
CC
V
CC
V
ON
C
LOAD
DISCHARGES
RAMP-DOWN
SLOPE = –50μA/C1
RAMP-UP
SLOPE = 10μA/C1
V
OUT
V
GATE
0V
0V
1647-1/2/3 F05
V
CC
+ Δ
V
GATE
V
CC
V
CC
V
CC
V
LKO
V
LKO
–
V
LKH
C
LOAD
DISCHARGES
V
CC
UNPLUGGED
OUT OF UVLO
INTO UVLO
FAST RAMP-DOWN
AT UNDERVOLTAGE
LOCKOUT
V
GATE
DROOP
DUE TO V
CC
RAMP-UP
SLOPE = 10μA/C1
V
OUT
V
GATE
0V
0V
1647-1/2/3 F06
Figure 5. Supply Turn-On/Off with ON
Figure 6. Supply Turn-On/Off with V
CC
SENSE
86
ON/FAULT
V
CC
V
OUT
FAULT
ON
(5V LOGIC)
2
GND
4
GATE
LTC1647-2
C1
10nF
R2
10Ω
R1
0.01Ω
Q1
IRF7413
C
LOAD
+
V
CC
1
R3
15k
C3
0.1μF
t
RESET
t
DELAY
t
RAMP
V
CC
– V
SENSE
V
GATE
V
FAULT
1647-1/2/3 F07
an input supply greater than 10V at V
CC1
or V
CC2
, a 24V
Zener is recommended between the corresponding GATE1
or GATE2 pin and GND as shown in Figures 1 and 4.
The R
DS(ON)
of the external pass transistor must be low to
make V
DS
a small percentage of V
CC
. At V
CC
= 3.3V, V
DS
+ V
CB
= 0.1V yields 3% error at maximum load current.
This restricts the choice of MOSFETs to very low R
DS(ON)
.
At higher V
CC
voltages, the R
DS(ON)
requirement can be
relaxed. MOSFET package dissipation (P
D
and T
J
) may
restrict the value of R
DS(ON)
.
Power Supply Ramping
V
OUT
is controlled by placing MOSFET Q1 in the power
path (Figure 1). R1 provides load current fault detection
and R2 prevents MOSFET high frequency oscillation. By
ramping the gate of the pass transistor at a controlled
rate (dV/dt = 10μA/C1), the transient surge current
(I = C
LOAD
•dV/dt = 10μA•C
LOAD
/C1) drawn from the main
backplane is limited to a safe value when the board is
inserted into the connector.
When power is first applied to V
CC
, the GATE pin pulls low.
A low-to-high transition at the ON pin initiates GATE ramp-
up. The rising dV/dt of GATE is set by 10μA/C1 (Figure 5),
where C1 is the total external capacitance between
GATE and GND. The ramp-up time for V
OUT
is equal to
t = (V
CC
•C1)/10μA.
A high-to-low transition at the ON pin initiates a GATE
ramp-down at a slope of –50μA/C1. This rate is usually
adequate as the supply bypass capacitors take time to
discharge through the load.
If the ON pin is connected to V
CC
, or is pulled high before
V
CC
is first applied, GATE is held low until V
CC
rises above
the undervoltage lockout threshold, V
LKO
(Figure 6). Once
the threshold is exceeded, GATE ramps at a controlled rate
of 10μA/C1. When the power supply is disconnected, the
body diode of Q1 holds V
CC
about 700mV below V
OUT
.
The GATE voltage droops at a rate determined by V
CC
. If
V
CC
drops below V
LKO
– V
LKH
, the LTC1647 enters UVLO
and GATE pulls down to GND.
Figure 7. Autoretry Sequence
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LTC1647-3IGN#PBF

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Buy LTC1647-3IGN#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers 2x Hot Swap Cntrs
Lifecycle:
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