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74HC7403N,112

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 4 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 5. Pin configuration
',5
*1'
2
+&
PJD
'25
62
05
9
&&
'
'
'
'
4
4
4
4
Table 2. Pin description
Symbol Pin Description
OE
1 output enable input (active LOW)
DIR 2 data-in-ready output
SI 3 shift-in input (active HIGH)
D0 to D3 4, 5, 6, 7 parallel data input
GND 8 ground (0 V)
MR
9 asynchronous master-reset input (active LOW)
Q0 to Q3 13, 12, 11, 10 data output
DOR 14 data-out-ready output
SO
15 shift-out input (active LOW)
V
CC
16 supply voltage
74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 5 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
7. Functional description
A DIR flag indicates the input stage status, either empty and ready to receive data (DIR =
HIGH) or full and busy (DIR = LOW). When DIR and SI are HIGH, data present at D0 to
D3 is shifted into the input stage; once complete DIR goes LOW. When SI is set LOW,
data is automatically shifted to the output stage or to the last empty location. DIR set
HIGH indicates a FIFO which can receive data.
A DOR flag indicates the output stage status, either data available (DOR = HIGH) or busy
(DOR = LOW). When SO
and DOR are HIGH, data is available at the outputs (Q0 to Q3).
When SO
is set LOW new data may be shifted into the output stage, once complete DOR
is set HIGH.
7.1 Expanded format
The DOR and DIR signals are used to allow the 74HC7403; 74HCT7403 to be cascaded.
Both parallel and serial expansion is possible. (see Figure 18
).
Serial expansion is only possible with typical devices.
7.1.1 Parallel expension
Parallel expension is accomplished by logically ANDing the DOR and DIR signals to form
a composite signal.
7.1.2 Serial expension
Serial expension is accomplished by:
• Tying the data outputs of the first device to the data inputs of the second device.
• Connecting the DOR pin of the first device to the SI pin of the second device.
• Connecting the SO pin of the first device to the DIR pin of the second device.
8. Limiting values
[1] For DIP16 packages: above 70 C the value of P
tot
derates linearly with 12 mW/K.
[2] For SO16 packages: above 70 C the value of P
tot
derates linearly with 8 mW/K.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V) - 35 mA
I
CC
supply current - +70 mA
I
GND
ground current - 70 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP16 package
[1]
- 750 mW
SO16 package
[2]
- 500 mW
74HC_HCT7403 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 24 September 2012 6 of 34
NXP Semiconductors
74HC7403; 74HCT7403
4-bit x 64-word FIFO register; 3-state
9. Recommended operating conditions
10. Static characteristics
Table 4. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC7403 74HCT7403 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0- V
CC
V
V
O
output voltage 0 - V
CC
0- V
CC
V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V--83---ns/V
Table 5. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC7403
V
IH
HIGH-level
input voltage
V
CC
= 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
V
CC
= 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
V
CC
= 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
V
CC
= 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
V
CC
= 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
V
OH
HIGH-level
output voltage
V
I
=V
IH
or V
IL
I
O
= 20 A; V
CC
= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
I
O
= 20 A; V
CC
= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
I
O
= 20 A; V
CC
= 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
I
O
= 8mA; V
CC
= 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
I
O
= 10 mA; V
CC
= 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
V
OL
LOW-level
output voltage
V
I
=V
IH
or V
IL
I
O
=20A; V
CC
= 2.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
=20A; V
CC
= 4.5 V - 0 0.1 - 0.1 - 0.1 V
I
O
=20A; V
CC
= 6.0 V - 0 0.1 - 0.1 - 0.1 V
I
O
= 8 mA; V
CC
= 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
I
O
=10mA; V
CC
= 6.0 V - 0.15 0.26 - 0.33 - 0.4 V
I
I
input leakage
current
V
I
=V
CC
or GND;
V
CC
=6.0V
--0.1 - 1.0 - 1.0 A
I
OZ
OFF-state
output current
V
I
=V
IH
or V
IL
;
V
O
=V
CC
or GND;
V
CC
=6.0V
--0.5 - 5.0 - 10.0 A
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74HC7403N,112

Mfr. #:
Buy 74HC7403N,112
Manufacturer:
NXP Semiconductors
Description:
Registers 4BX64W FIFO REGISTER
Lifecycle:
New from this manufacturer.
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